faults.cc (3521:0b0b3551def0) faults.cc (4172:141705d83494)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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121
122void AlphaFault::invoke(ThreadContext * tc)
123{
124 FaultBase::invoke(tc);
125 countStat()++;
126
127 // exception restart address
128 if (setRestartAddress() || !(tc->readPC() & 0x3))
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 112 unchanged lines hidden (view full) ---

121
122void AlphaFault::invoke(ThreadContext * tc)
123{
124 FaultBase::invoke(tc);
125 countStat()++;
126
127 // exception restart address
128 if (setRestartAddress() || !(tc->readPC() & 0x3))
129 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
129 tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC());
130
131 if (skipFaultingInstruction()) {
132 // traps... skip faulting instruction.
130
131 if (skipFaultingInstruction()) {
132 // traps... skip faulting instruction.
133 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
134 tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
133 tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
134 tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4);
135 }
136
135 }
136
137 tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
137 tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect());
138 tc->setNextPC(tc->readPC() + sizeof(MachInst));
139}
140
141void ArithmeticFault::invoke(ThreadContext * tc)
142{
143 FaultBase::invoke(tc);
144 panic("Arithmetic traps are unimplemented!");
145}
146
147void DtbFault::invoke(ThreadContext * tc)
148{
149 // Set fault address and flags. Even though we're modeling an
150 // EV5, we use the EV6 technique of not latching fault registers
151 // on VPTE loads (instead of locking the registers until IPR_VA is
152 // read, like the EV5). The EV6 approach is cleaner and seems to
153 // work with EV5 PAL code, but not the other way around.
154 if (!tc->misspeculating()
155 && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
156 // set VA register with faulting address
138 tc->setNextPC(tc->readPC() + sizeof(MachInst));
139}
140
141void ArithmeticFault::invoke(ThreadContext * tc)
142{
143 FaultBase::invoke(tc);
144 panic("Arithmetic traps are unimplemented!");
145}
146
147void DtbFault::invoke(ThreadContext * tc)
148{
149 // Set fault address and flags. Even though we're modeling an
150 // EV5, we use the EV6 technique of not latching fault registers
151 // on VPTE loads (instead of locking the registers until IPR_VA is
152 // read, like the EV5). The EV6 approach is cleaner and seems to
153 // work with EV5 PAL code, but not the other way around.
154 if (!tc->misspeculating()
155 && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
156 // set VA register with faulting address
157 tc->setMiscReg(AlphaISA::IPR_VA, vaddr);
157 tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr);
158
159 // set MM_STAT register flags
158
159 // set MM_STAT register flags
160 tc->setMiscReg(AlphaISA::IPR_MM_STAT,
160 tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
161 (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
162 | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
163 | (flags & 0x3f)));
164
165 // set VA_FORM register with faulting formatted address
161 (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
162 | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
163 | (flags & 0x3f)));
164
165 // set VA_FORM register with faulting formatted address
166 tc->setMiscReg(AlphaISA::IPR_VA_FORM,
167 tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
166 tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM,
167 tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
168 }
169
170 AlphaFault::invoke(tc);
171}
172
173void ItbFault::invoke(ThreadContext * tc)
174{
175 if (!tc->misspeculating()) {
168 }
169
170 AlphaFault::invoke(tc);
171}
172
173void ItbFault::invoke(ThreadContext * tc)
174{
175 if (!tc->misspeculating()) {
176 tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
177 tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
178 tc->readMiscReg(AlphaISA::IPR_IVPTBR) |
176 tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc);
177 tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM,
178 tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) |
179 (AlphaISA::VAddr(pc).vpn() << 3));
180 }
181
182 AlphaFault::invoke(tc);
183}
184
185#else //!FULL_SYSTEM
186

--- 28 unchanged lines hidden --- 		179 (AlphaISA::VAddr(pc).vpn() << 3));
180 }
181
182 AlphaFault::invoke(tc);
183}
184
185#else //!FULL_SYSTEM
186

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