faults.cc (3363:8ed27e349b3d) faults.cc (3521:0b0b3551def0)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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120#if FULL_SYSTEM
121
122void AlphaFault::invoke(ThreadContext * tc)
123{
124 FaultBase::invoke(tc);
125 countStat()++;
126
127 // exception restart address
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 111 unchanged lines hidden (view full) ---

120#if FULL_SYSTEM
121
122void AlphaFault::invoke(ThreadContext * tc)
123{
124 FaultBase::invoke(tc);
125 countStat()++;
126
127 // exception restart address
128 if (setRestartAddress() || !tc->inPalMode())
128 if (setRestartAddress() || !(tc->readPC() & 0x3))
129 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
130
131 if (skipFaultingInstruction()) {
132 // traps... skip faulting instruction.
133 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
134 tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
135 }
136

--- 78 unchanged lines hidden --- 		129 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
130
131 if (skipFaultingInstruction()) {
132 // traps... skip faulting instruction.
133 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
134 tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
135 }
136

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