faults.cc (2680:246e7104f744) | faults.cc (2800:18a615ca6e19) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 21 unchanged lines hidden (view full) --- 30 */ 31 32#include "arch/alpha/faults.hh" 33#include "cpu/thread_context.hh" 34#include "cpu/base.hh" 35#include "base/trace.hh" 36#if FULL_SYSTEM 37#include "arch/alpha/ev5.hh" | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 21 unchanged lines hidden (view full) --- 30 */ 31 32#include "arch/alpha/faults.hh" 33#include "cpu/thread_context.hh" 34#include "cpu/base.hh" 35#include "base/trace.hh" 36#if FULL_SYSTEM 37#include "arch/alpha/ev5.hh" |
38#else 39#include "sim/process.hh" 40#include "mem/page_table.hh" |
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38#endif 39 40namespace AlphaISA 41{ 42 43FaultName MachineCheckFault::_name = "mchk"; 44FaultVect MachineCheckFault::_vect = 0x0401; 45FaultStat MachineCheckFault::_count; --- 5 unchanged lines hidden (view full) --- 51FaultName ResetFault::_name = "reset"; 52FaultVect ResetFault::_vect = 0x0001; 53FaultStat ResetFault::_count; 54 55FaultName ArithmeticFault::_name = "arith"; 56FaultVect ArithmeticFault::_vect = 0x0501; 57FaultStat ArithmeticFault::_count; 58 | 41#endif 42 43namespace AlphaISA 44{ 45 46FaultName MachineCheckFault::_name = "mchk"; 47FaultVect MachineCheckFault::_vect = 0x0401; 48FaultStat MachineCheckFault::_count; --- 5 unchanged lines hidden (view full) --- 54FaultName ResetFault::_name = "reset"; 55FaultVect ResetFault::_vect = 0x0001; 56FaultStat ResetFault::_count; 57 58FaultName ArithmeticFault::_name = "arith"; 59FaultVect ArithmeticFault::_vect = 0x0501; 60FaultStat ArithmeticFault::_count; 61 |
62#if !FULL_SYSTEM 63FaultName PageTableFault::_name = "page_table_fault"; 64FaultVect PageTableFault::_vect = 0x0000; 65FaultStat PageTableFault::_count; 66#endif 67 |
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59FaultName InterruptFault::_name = "interrupt"; 60FaultVect InterruptFault::_vect = 0x0101; 61FaultStat InterruptFault::_count; 62 63FaultName NDtbMissFault::_name = "dtb_miss_single"; 64FaultVect NDtbMissFault::_vect = 0x0201; 65FaultStat NDtbMissFault::_count; 66 --- 101 unchanged lines hidden (view full) --- 168 tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, 169 tc->readMiscReg(AlphaISA::IPR_IVPTBR) | 170 (AlphaISA::VAddr(pc).vpn() << 3)); 171 } 172 173 AlphaFault::invoke(tc); 174} 175 | 68FaultName InterruptFault::_name = "interrupt"; 69FaultVect InterruptFault::_vect = 0x0101; 70FaultStat InterruptFault::_count; 71 72FaultName NDtbMissFault::_name = "dtb_miss_single"; 73FaultVect NDtbMissFault::_vect = 0x0201; 74FaultStat NDtbMissFault::_count; 75 --- 101 unchanged lines hidden (view full) --- 177 tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, 178 tc->readMiscReg(AlphaISA::IPR_IVPTBR) | 179 (AlphaISA::VAddr(pc).vpn() << 3)); 180 } 181 182 AlphaFault::invoke(tc); 183} 184 |
185#else //!FULL_SYSTEM 186 187void PageTableFault::invoke(ThreadContext *tc) 188{ 189 Process *p = tc->getProcessPtr(); 190 191 // address is higher than the stack region or in the current stack region 192 if (vaddr > p->stack_base || vaddr > p->stack_min) 193 FaultBase::invoke(tc); 194 195 // We've accessed the next page 196 if (vaddr > p->stack_min - PageBytes) { 197 p->stack_min -= PageBytes; 198 if (p->stack_base - p->stack_min > 8*1024*1024) 199 fatal("Over max stack size for one thread\n"); 200 p->pTable->allocate(p->stack_min, PageBytes); 201 warn("Increasing stack size by one page."); 202 } else { 203 FaultBase::invoke(tc); 204 } 205} 206 |
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176#endif 177 178} // namespace AlphaISA 179 | 207#endif 208 209} // namespace AlphaISA 210 |