faults.cc (2665:a124942bacb8) faults.cc (2680:246e7104f744)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include "arch/alpha/faults.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 16 unchanged lines hidden (view full) ---

25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include "arch/alpha/faults.hh"
33#include "cpu/exec_context.hh"
33#include "cpu/thread_context.hh"
34#include "cpu/base.hh"
35#include "base/trace.hh"
36#if FULL_SYSTEM
37#include "arch/alpha/ev5.hh"
38#endif
39
40namespace AlphaISA
41{

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105FaultStat PalFault::_count;
106
107FaultName IntegerOverflowFault::_name = "intover";
108FaultVect IntegerOverflowFault::_vect = 0x0501;
109FaultStat IntegerOverflowFault::_count;
110
111#if FULL_SYSTEM
112
34#include "cpu/base.hh"
35#include "base/trace.hh"
36#if FULL_SYSTEM
37#include "arch/alpha/ev5.hh"
38#endif
39
40namespace AlphaISA
41{

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105FaultStat PalFault::_count;
106
107FaultName IntegerOverflowFault::_name = "intover";
108FaultVect IntegerOverflowFault::_vect = 0x0501;
109FaultStat IntegerOverflowFault::_count;
110
111#if FULL_SYSTEM
112
113void AlphaFault::invoke(ExecContext * xc)
113void AlphaFault::invoke(ThreadContext * tc)
114{
114{
115 FaultBase::invoke(xc);
115 FaultBase::invoke(tc);
116 countStat()++;
117
118 // exception restart address
116 countStat()++;
117
118 // exception restart address
119 if (setRestartAddress() || !xc->inPalMode())
120 xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC());
119 if (setRestartAddress() || !tc->inPalMode())
120 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
121
122 if (skipFaultingInstruction()) {
123 // traps... skip faulting instruction.
121
122 if (skipFaultingInstruction()) {
123 // traps... skip faulting instruction.
124 xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
125 xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
124 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
125 tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
126 }
127
126 }
127
128 xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
129 xc->setNextPC(xc->readPC() + sizeof(MachInst));
128 tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
129 tc->setNextPC(tc->readPC() + sizeof(MachInst));
130}
131
130}
131
132void ArithmeticFault::invoke(ExecContext * xc)
132void ArithmeticFault::invoke(ThreadContext * tc)
133{
133{
134 FaultBase::invoke(xc);
134 FaultBase::invoke(tc);
135 panic("Arithmetic traps are unimplemented!");
136}
137
135 panic("Arithmetic traps are unimplemented!");
136}
137
138void DtbFault::invoke(ExecContext * xc)
138void DtbFault::invoke(ThreadContext * tc)
139{
140 // Set fault address and flags. Even though we're modeling an
141 // EV5, we use the EV6 technique of not latching fault registers
142 // on VPTE loads (instead of locking the registers until IPR_VA is
143 // read, like the EV5). The EV6 approach is cleaner and seems to
144 // work with EV5 PAL code, but not the other way around.
139{
140 // Set fault address and flags. Even though we're modeling an
141 // EV5, we use the EV6 technique of not latching fault registers
142 // on VPTE loads (instead of locking the registers until IPR_VA is
143 // read, like the EV5). The EV6 approach is cleaner and seems to
144 // work with EV5 PAL code, but not the other way around.
145 if (!xc->misspeculating()
145 if (!tc->misspeculating()
146 && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
147 // set VA register with faulting address
146 && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
147 // set VA register with faulting address
148 xc->setMiscReg(AlphaISA::IPR_VA, vaddr);
148 tc->setMiscReg(AlphaISA::IPR_VA, vaddr);
149
150 // set MM_STAT register flags
149
150 // set MM_STAT register flags
151 xc->setMiscReg(AlphaISA::IPR_MM_STAT,
152 (((EV5::Opcode(xc->getInst()) & 0x3f) << 11)
153 | ((EV5::Ra(xc->getInst()) & 0x1f) << 6)
151 tc->setMiscReg(AlphaISA::IPR_MM_STAT,
152 (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
153 | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
154 | (flags & 0x3f)));
155
156 // set VA_FORM register with faulting formatted address
154 | (flags & 0x3f)));
155
156 // set VA_FORM register with faulting formatted address
157 xc->setMiscReg(AlphaISA::IPR_VA_FORM,
158 xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
157 tc->setMiscReg(AlphaISA::IPR_VA_FORM,
158 tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
159 }
160
159 }
160
161 AlphaFault::invoke(xc);
161 AlphaFault::invoke(tc);
162}
163
162}
163
164void ItbFault::invoke(ExecContext * xc)
164void ItbFault::invoke(ThreadContext * tc)
165{
165{
166 if (!xc->misspeculating()) {
167 xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
168 xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
169 xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
166 if (!tc->misspeculating()) {
167 tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
168 tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
169 tc->readMiscReg(AlphaISA::IPR_IVPTBR) |
170 (AlphaISA::VAddr(pc).vpn() << 3));
171 }
172
170 (AlphaISA::VAddr(pc).vpn() << 3));
171 }
172
173 AlphaFault::invoke(xc);
173 AlphaFault::invoke(tc);
174}
175
176#endif
177
178} // namespace AlphaISA
179
174}
175
176#endif
177
178} // namespace AlphaISA
179