faults.cc (10664:61a0b02aa800) faults.cc (10823:64cd1dcd61a5)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 133 unchanged lines hidden (view full) ---

142DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
143{
144 if (FullSystem) {
145 // Set fault address and flags. Even though we're modeling an
146 // EV5, we use the EV6 technique of not latching fault registers
147 // on VPTE loads (instead of locking the registers until IPR_VA is
148 // read, like the EV5). The EV6 approach is cleaner and seems to
149 // work with EV5 PAL code, but not the other way around.
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 133 unchanged lines hidden (view full) ---

142DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
143{
144 if (FullSystem) {
145 // Set fault address and flags. Even though we're modeling an
146 // EV5, we use the EV6 technique of not latching fault registers
147 // on VPTE loads (instead of locking the registers until IPR_VA is
148 // read, like the EV5). The EV6 approach is cleaner and seems to
149 // work with EV5 PAL code, but not the other way around.
150 if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
150 if (reqFlags.noneSet(AlphaRequestFlags::VPTE | Request::PREFETCH)) {
151 // set VA register with faulting address
152 tc->setMiscRegNoEffect(IPR_VA, vaddr);
153
154 // set MM_STAT register flags
155 MachInst machInst = inst->machInst;
156 tc->setMiscRegNoEffect(IPR_MM_STAT,
157 (((Opcode(machInst) & 0x3f) << 11) |
158 ((Ra(machInst) & 0x1f) << 6) |

--- 66 unchanged lines hidden --- 		151 // set VA register with faulting address
152 tc->setMiscRegNoEffect(IPR_VA, vaddr);
153
154 // set MM_STAT register flags
155 MachInst machInst = inst->machInst;
156 tc->setMiscRegNoEffect(IPR_MM_STAT,
157 (((Opcode(machInst) & 0x3f) << 11) |
158 ((Ra(machInst) & 0x1f) << 6) |

--- 66 unchanged lines hidden ---