faults.cc (10417:710ee116eb68) faults.cc (10664:61a0b02aa800)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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142DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
143{
144 if (FullSystem) {
145 // Set fault address and flags. Even though we're modeling an
146 // EV5, we use the EV6 technique of not latching fault registers
147 // on VPTE loads (instead of locking the registers until IPR_VA is
148 // read, like the EV5). The EV6 approach is cleaner and seems to
149 // work with EV5 PAL code, but not the other way around.
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 133 unchanged lines hidden (view full) ---

142DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
143{
144 if (FullSystem) {
145 // Set fault address and flags. Even though we're modeling an
146 // EV5, we use the EV6 technique of not latching fault registers
147 // on VPTE loads (instead of locking the registers until IPR_VA is
148 // read, like the EV5). The EV6 approach is cleaner and seems to
149 // work with EV5 PAL code, but not the other way around.
150 if (!tc->misspeculating() &&
151 reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
150 if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
152 // set VA register with faulting address
153 tc->setMiscRegNoEffect(IPR_VA, vaddr);
154
155 // set MM_STAT register flags
156 MachInst machInst = inst->machInst;
157 tc->setMiscRegNoEffect(IPR_MM_STAT,
158 (((Opcode(machInst) & 0x3f) << 11) |
159 ((Ra(machInst) & 0x1f) << 6) |

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167
168 AlphaFault::invoke(tc);
169}
170
171void
172ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
173{
174 if (FullSystem) {
151 // set VA register with faulting address
152 tc->setMiscRegNoEffect(IPR_VA, vaddr);
153
154 // set MM_STAT register flags
155 MachInst machInst = inst->machInst;
156 tc->setMiscRegNoEffect(IPR_MM_STAT,
157 (((Opcode(machInst) & 0x3f) << 11) |
158 ((Ra(machInst) & 0x1f) << 6) |

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166
167 AlphaFault::invoke(tc);
168}
169
170void
171ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
172{
173 if (FullSystem) {
175 if (!tc->misspeculating()) {
176 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
177 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
178 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
179 }
174 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
175 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
176 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
180 }
181
182 AlphaFault::invoke(tc);
183}
184
185void
186ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
187{

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178
179 AlphaFault::invoke(tc);
180}
181
182void
183ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
184{

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