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<
< #if !FULL_SYSTEM
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< #endif
---
> #include "sim/full_system.hh"
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< #if FULL_SYSTEM
<
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> if (!FullSystem)
> return;
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> if (!FullSystem)
> return;
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< // Set fault address and flags. Even though we're modeling an
< // EV5, we use the EV6 technique of not latching fault registers
< // on VPTE loads (instead of locking the registers until IPR_VA is
< // read, like the EV5). The EV6 approach is cleaner and seems to
< // work with EV5 PAL code, but not the other way around.
< if (!tc->misspeculating() &&
< reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
< // set VA register with faulting address
< tc->setMiscRegNoEffect(IPR_VA, vaddr);
---
> if (FullSystem) {
> // Set fault address and flags. Even though we're modeling an
> // EV5, we use the EV6 technique of not latching fault registers
> // on VPTE loads (instead of locking the registers until IPR_VA is
> // read, like the EV5). The EV6 approach is cleaner and seems to
> // work with EV5 PAL code, but not the other way around.
> if (!tc->misspeculating() &&
> reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
> // set VA register with faulting address
> tc->setMiscRegNoEffect(IPR_VA, vaddr);
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< // set MM_STAT register flags
< MachInst machInst = inst->machInst;
< tc->setMiscRegNoEffect(IPR_MM_STAT,
< (((Opcode(machInst) & 0x3f) << 11) |
< ((Ra(machInst) & 0x1f) << 6) |
< (flags & 0x3f)));
---
> // set MM_STAT register flags
> MachInst machInst = inst->machInst;
> tc->setMiscRegNoEffect(IPR_MM_STAT,
> (((Opcode(machInst) & 0x3f) << 11) |
> ((Ra(machInst) & 0x1f) << 6) |
> (flags & 0x3f)));
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< // set VA_FORM register with faulting formatted address
< tc->setMiscRegNoEffect(IPR_VA_FORM,
< tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
---
> // set VA_FORM register with faulting formatted address
> tc->setMiscRegNoEffect(IPR_VA_FORM,
> tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
> }
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< if (!tc->misspeculating()) {
< tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
< tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
< tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
---
> if (FullSystem) {
> if (!tc->misspeculating()) {
> tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
> tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
> tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
> }
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< #else
<
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< Process *p = tc->getProcessPtr();
< TlbEntry entry;
< bool success = p->pTable->lookup(pc, entry);
< if (!success) {
< panic("Tried to execute unmapped address %#x.\n", pc);
---
> if (FullSystem) {
> ItbFault::invoke(tc);
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< VAddr vaddr(pc);
< tc->getITBPtr()->insert(vaddr.page(), entry);
---
> Process *p = tc->getProcessPtr();
> TlbEntry entry;
> bool success = p->pTable->lookup(pc, entry);
> if (!success) {
> panic("Tried to execute unmapped address %#x.\n", pc);
> } else {
> VAddr vaddr(pc);
> tc->getITBPtr()->insert(vaddr.page(), entry);
> }
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< Process *p = tc->getProcessPtr();
< TlbEntry entry;
< bool success = p->pTable->lookup(vaddr, entry);
< if (!success) {
< if (p->fixupStackFault(vaddr))
< success = p->pTable->lookup(vaddr, entry);
< }
< if (!success) {
< panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
---
> if (FullSystem) {
> DtbFault::invoke(tc, inst);
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< tc->getDTBPtr()->insert(vaddr.page(), entry);
---
> Process *p = tc->getProcessPtr();
> TlbEntry entry;
> bool success = p->pTable->lookup(vaddr, entry);
> if (!success) {
> if (p->fixupStackFault(vaddr))
> success = p->pTable->lookup(vaddr, entry);
> }
> if (!success) {
> panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
> } else {
> tc->getDTBPtr()->insert(vaddr.page(), entry);
> }
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< #endif
<