33c33
< #include "cpu/exec_context.hh"
---
> #include "cpu/thread_context.hh"
113c113
< void AlphaFault::invoke(ExecContext * xc)
---
> void AlphaFault::invoke(ThreadContext * tc)
115c115
< FaultBase::invoke(xc);
---
> FaultBase::invoke(tc);
119,120c119,120
< if (setRestartAddress() || !xc->inPalMode())
< xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC());
---
> if (setRestartAddress() || !tc->inPalMode())
> tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
124,125c124,125
< xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
< xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
---
> tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
> tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
128,129c128,129
< xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
< xc->setNextPC(xc->readPC() + sizeof(MachInst));
---
> tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
> tc->setNextPC(tc->readPC() + sizeof(MachInst));
132c132
< void ArithmeticFault::invoke(ExecContext * xc)
---
> void ArithmeticFault::invoke(ThreadContext * tc)
134c134
< FaultBase::invoke(xc);
---
> FaultBase::invoke(tc);
138c138
< void DtbFault::invoke(ExecContext * xc)
---
> void DtbFault::invoke(ThreadContext * tc)
145c145
< if (!xc->misspeculating()
---
> if (!tc->misspeculating()
148c148
< xc->setMiscReg(AlphaISA::IPR_VA, vaddr);
---
> tc->setMiscReg(AlphaISA::IPR_VA, vaddr);
151,153c151,153
< xc->setMiscReg(AlphaISA::IPR_MM_STAT,
< (((EV5::Opcode(xc->getInst()) & 0x3f) << 11)
< | ((EV5::Ra(xc->getInst()) & 0x1f) << 6)
---
> tc->setMiscReg(AlphaISA::IPR_MM_STAT,
> (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
> | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
157,158c157,158
< xc->setMiscReg(AlphaISA::IPR_VA_FORM,
< xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
---
> tc->setMiscReg(AlphaISA::IPR_VA_FORM,
> tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
161c161
< AlphaFault::invoke(xc);
---
> AlphaFault::invoke(tc);
164c164
< void ItbFault::invoke(ExecContext * xc)
---
> void ItbFault::invoke(ThreadContext * tc)
166,169c166,169
< if (!xc->misspeculating()) {
< xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
< xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
< xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
---
> if (!tc->misspeculating()) {
> tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
> tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
> tc->readMiscReg(AlphaISA::IPR_IVPTBR) |
173c173
< AlphaFault::invoke(xc);
---
> AlphaFault::invoke(tc);