1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include "arch/alpha/ev5.hh"
33#include "arch/alpha/faults.hh"
34#include "arch/alpha/tlb.hh"
35#include "base/trace.hh"
36#include "cpu/base.hh"
37#include "cpu/thread_context.hh"
38
39#if !FULL_SYSTEM
40#include "mem/page_table.hh"
41#include "sim/process.hh"
42#endif
43
44namespace AlphaISA {
45
46FaultName MachineCheckFault::_name = "mchk";
47FaultVect MachineCheckFault::_vect = 0x0401;
48FaultStat MachineCheckFault::_count;
49
50FaultName AlignmentFault::_name = "unalign";
51FaultVect AlignmentFault::_vect = 0x0301;
52FaultStat AlignmentFault::_count;
53
54FaultName ResetFault::_name = "reset";
55FaultVect ResetFault::_vect = 0x0001;
56FaultStat ResetFault::_count;
57
58FaultName ArithmeticFault::_name = "arith";
59FaultVect ArithmeticFault::_vect = 0x0501;
60FaultStat ArithmeticFault::_count;
61
62FaultName InterruptFault::_name = "interrupt";
63FaultVect InterruptFault::_vect = 0x0101;
64FaultStat InterruptFault::_count;
65
66FaultName NDtbMissFault::_name = "dtb_miss_single";
67FaultVect NDtbMissFault::_vect = 0x0201;
68FaultStat NDtbMissFault::_count;
69
70FaultName PDtbMissFault::_name = "dtb_miss_double";
71FaultVect PDtbMissFault::_vect = 0x0281;
72FaultStat PDtbMissFault::_count;
73
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include "arch/alpha/ev5.hh"
33#include "arch/alpha/faults.hh"
34#include "arch/alpha/tlb.hh"
35#include "base/trace.hh"
36#include "cpu/base.hh"
37#include "cpu/thread_context.hh"
38
39#if !FULL_SYSTEM
40#include "mem/page_table.hh"
41#include "sim/process.hh"
42#endif
43
44namespace AlphaISA {
45
46FaultName MachineCheckFault::_name = "mchk";
47FaultVect MachineCheckFault::_vect = 0x0401;
48FaultStat MachineCheckFault::_count;
49
50FaultName AlignmentFault::_name = "unalign";
51FaultVect AlignmentFault::_vect = 0x0301;
52FaultStat AlignmentFault::_count;
53
54FaultName ResetFault::_name = "reset";
55FaultVect ResetFault::_vect = 0x0001;
56FaultStat ResetFault::_count;
57
58FaultName ArithmeticFault::_name = "arith";
59FaultVect ArithmeticFault::_vect = 0x0501;
60FaultStat ArithmeticFault::_count;
61
62FaultName InterruptFault::_name = "interrupt";
63FaultVect InterruptFault::_vect = 0x0101;
64FaultStat InterruptFault::_count;
65
66FaultName NDtbMissFault::_name = "dtb_miss_single";
67FaultVect NDtbMissFault::_vect = 0x0201;
68FaultStat NDtbMissFault::_count;
69
70FaultName PDtbMissFault::_name = "dtb_miss_double";
71FaultVect PDtbMissFault::_vect = 0x0281;
72FaultStat PDtbMissFault::_count;
73
|
74FaultName DtbPageFault::_name = "dfault";
| 74FaultName DtbPageFault::_name = "dtb_page_fault";
|
75FaultVect DtbPageFault::_vect = 0x0381;
76FaultStat DtbPageFault::_count;
77
| 75FaultVect DtbPageFault::_vect = 0x0381;
76FaultStat DtbPageFault::_count;
77
|
78FaultName DtbAcvFault::_name = "dfault";
| 78FaultName DtbAcvFault::_name = "dtb_acv_fault";
|
79FaultVect DtbAcvFault::_vect = 0x0381;
80FaultStat DtbAcvFault::_count;
81
82FaultName DtbAlignmentFault::_name = "unalign";
83FaultVect DtbAlignmentFault::_vect = 0x0301;
84FaultStat DtbAlignmentFault::_count;
85
86FaultName ItbPageFault::_name = "itbmiss";
87FaultVect ItbPageFault::_vect = 0x0181;
88FaultStat ItbPageFault::_count;
89
90FaultName ItbAcvFault::_name = "iaccvio";
91FaultVect ItbAcvFault::_vect = 0x0081;
92FaultStat ItbAcvFault::_count;
93
94FaultName UnimplementedOpcodeFault::_name = "opdec";
95FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
96FaultStat UnimplementedOpcodeFault::_count;
97
98FaultName FloatEnableFault::_name = "fen";
99FaultVect FloatEnableFault::_vect = 0x0581;
100FaultStat FloatEnableFault::_count;
101
102FaultName PalFault::_name = "pal";
103FaultVect PalFault::_vect = 0x2001;
104FaultStat PalFault::_count;
105
106FaultName IntegerOverflowFault::_name = "intover";
107FaultVect IntegerOverflowFault::_vect = 0x0501;
108FaultStat IntegerOverflowFault::_count;
109
110#if FULL_SYSTEM
111
112void
113AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
114{
115 FaultBase::invoke(tc);
116 countStat()++;
117
118 PCState pc = tc->pcState();
119
120 // exception restart address
121 if (setRestartAddress() || !(pc.pc() & 0x3))
122 tc->setMiscRegNoEffect(IPR_EXC_ADDR, pc.pc());
123
124 if (skipFaultingInstruction()) {
125 // traps... skip faulting instruction.
126 tc->setMiscRegNoEffect(IPR_EXC_ADDR,
127 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
128 }
129
130 pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
131 tc->pcState(pc);
132}
133
134void
135ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
136{
137 FaultBase::invoke(tc);
138 panic("Arithmetic traps are unimplemented!");
139}
140
141void
142DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
143{
144 // Set fault address and flags. Even though we're modeling an
145 // EV5, we use the EV6 technique of not latching fault registers
146 // on VPTE loads (instead of locking the registers until IPR_VA is
147 // read, like the EV5). The EV6 approach is cleaner and seems to
148 // work with EV5 PAL code, but not the other way around.
149 if (!tc->misspeculating() &&
150 reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
151 // set VA register with faulting address
152 tc->setMiscRegNoEffect(IPR_VA, vaddr);
153
154 // set MM_STAT register flags
155 MachInst machInst = inst->machInst;
156 tc->setMiscRegNoEffect(IPR_MM_STAT,
157 (((Opcode(machInst) & 0x3f) << 11) |
158 ((Ra(machInst) & 0x1f) << 6) |
159 (flags & 0x3f)));
160
161 // set VA_FORM register with faulting formatted address
162 tc->setMiscRegNoEffect(IPR_VA_FORM,
163 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
164 }
165
166 AlphaFault::invoke(tc);
167}
168
169void
170ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
171{
172 if (!tc->misspeculating()) {
173 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
174 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
175 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
176 }
177
178 AlphaFault::invoke(tc);
179}
180
181#else
182
183void
184ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
185{
186 Process *p = tc->getProcessPtr();
187 TlbEntry entry;
188 bool success = p->pTable->lookup(pc, entry);
189 if (!success) {
190 panic("Tried to execute unmapped address %#x.\n", pc);
191 } else {
192 VAddr vaddr(pc);
193 tc->getITBPtr()->insert(vaddr.page(), entry);
194 }
195}
196
197void
198NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
199{
200 Process *p = tc->getProcessPtr();
201 TlbEntry entry;
202 bool success = p->pTable->lookup(vaddr, entry);
203 if (!success) {
204 p->checkAndAllocNextPage(vaddr);
205 success = p->pTable->lookup(vaddr, entry);
206 }
207 if (!success) {
208 panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
209 } else {
210 tc->getDTBPtr()->insert(vaddr.page(), entry);
211 }
212}
213
214#endif
215
216} // namespace AlphaISA
217
| 79FaultVect DtbAcvFault::_vect = 0x0381;
80FaultStat DtbAcvFault::_count;
81
82FaultName DtbAlignmentFault::_name = "unalign";
83FaultVect DtbAlignmentFault::_vect = 0x0301;
84FaultStat DtbAlignmentFault::_count;
85
86FaultName ItbPageFault::_name = "itbmiss";
87FaultVect ItbPageFault::_vect = 0x0181;
88FaultStat ItbPageFault::_count;
89
90FaultName ItbAcvFault::_name = "iaccvio";
91FaultVect ItbAcvFault::_vect = 0x0081;
92FaultStat ItbAcvFault::_count;
93
94FaultName UnimplementedOpcodeFault::_name = "opdec";
95FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
96FaultStat UnimplementedOpcodeFault::_count;
97
98FaultName FloatEnableFault::_name = "fen";
99FaultVect FloatEnableFault::_vect = 0x0581;
100FaultStat FloatEnableFault::_count;
101
102FaultName PalFault::_name = "pal";
103FaultVect PalFault::_vect = 0x2001;
104FaultStat PalFault::_count;
105
106FaultName IntegerOverflowFault::_name = "intover";
107FaultVect IntegerOverflowFault::_vect = 0x0501;
108FaultStat IntegerOverflowFault::_count;
109
110#if FULL_SYSTEM
111
112void
113AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
114{
115 FaultBase::invoke(tc);
116 countStat()++;
117
118 PCState pc = tc->pcState();
119
120 // exception restart address
121 if (setRestartAddress() || !(pc.pc() & 0x3))
122 tc->setMiscRegNoEffect(IPR_EXC_ADDR, pc.pc());
123
124 if (skipFaultingInstruction()) {
125 // traps... skip faulting instruction.
126 tc->setMiscRegNoEffect(IPR_EXC_ADDR,
127 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
128 }
129
130 pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
131 tc->pcState(pc);
132}
133
134void
135ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
136{
137 FaultBase::invoke(tc);
138 panic("Arithmetic traps are unimplemented!");
139}
140
141void
142DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
143{
144 // Set fault address and flags. Even though we're modeling an
145 // EV5, we use the EV6 technique of not latching fault registers
146 // on VPTE loads (instead of locking the registers until IPR_VA is
147 // read, like the EV5). The EV6 approach is cleaner and seems to
148 // work with EV5 PAL code, but not the other way around.
149 if (!tc->misspeculating() &&
150 reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
151 // set VA register with faulting address
152 tc->setMiscRegNoEffect(IPR_VA, vaddr);
153
154 // set MM_STAT register flags
155 MachInst machInst = inst->machInst;
156 tc->setMiscRegNoEffect(IPR_MM_STAT,
157 (((Opcode(machInst) & 0x3f) << 11) |
158 ((Ra(machInst) & 0x1f) << 6) |
159 (flags & 0x3f)));
160
161 // set VA_FORM register with faulting formatted address
162 tc->setMiscRegNoEffect(IPR_VA_FORM,
163 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
164 }
165
166 AlphaFault::invoke(tc);
167}
168
169void
170ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
171{
172 if (!tc->misspeculating()) {
173 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
174 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
175 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
176 }
177
178 AlphaFault::invoke(tc);
179}
180
181#else
182
183void
184ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
185{
186 Process *p = tc->getProcessPtr();
187 TlbEntry entry;
188 bool success = p->pTable->lookup(pc, entry);
189 if (!success) {
190 panic("Tried to execute unmapped address %#x.\n", pc);
191 } else {
192 VAddr vaddr(pc);
193 tc->getITBPtr()->insert(vaddr.page(), entry);
194 }
195}
196
197void
198NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
199{
200 Process *p = tc->getProcessPtr();
201 TlbEntry entry;
202 bool success = p->pTable->lookup(vaddr, entry);
203 if (!success) {
204 p->checkAndAllocNextPage(vaddr);
205 success = p->pTable->lookup(vaddr, entry);
206 }
207 if (!success) {
208 panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
209 } else {
210 tc->getDTBPtr()->insert(vaddr.page(), entry);
211 }
212}
213
214#endif
215
216} // namespace AlphaISA
217
|