1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include "arch/alpha/ev5.hh"
33#include "arch/alpha/faults.hh"
34#include "arch/alpha/tlb.hh"
35#include "cpu/thread_context.hh"
36#include "cpu/base.hh"
37#include "base/trace.hh"
38#if !FULL_SYSTEM
39#include "sim/process.hh"
40#include "mem/page_table.hh"
41#endif
42
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include "arch/alpha/ev5.hh"
33#include "arch/alpha/faults.hh"
34#include "arch/alpha/tlb.hh"
35#include "cpu/thread_context.hh"
36#include "cpu/base.hh"
37#include "base/trace.hh"
38#if !FULL_SYSTEM
39#include "sim/process.hh"
40#include "mem/page_table.hh"
41#endif
42
|
43namespace AlphaISA
44{
| 43namespace AlphaISA {
|
45
46FaultName MachineCheckFault::_name = "mchk";
47FaultVect MachineCheckFault::_vect = 0x0401;
48FaultStat MachineCheckFault::_count;
49
50FaultName AlignmentFault::_name = "unalign";
51FaultVect AlignmentFault::_vect = 0x0301;
52FaultStat AlignmentFault::_count;
53
54FaultName ResetFault::_name = "reset";
55FaultVect ResetFault::_vect = 0x0001;
56FaultStat ResetFault::_count;
57
58FaultName ArithmeticFault::_name = "arith";
59FaultVect ArithmeticFault::_vect = 0x0501;
60FaultStat ArithmeticFault::_count;
61
62FaultName InterruptFault::_name = "interrupt";
63FaultVect InterruptFault::_vect = 0x0101;
64FaultStat InterruptFault::_count;
65
66FaultName NDtbMissFault::_name = "dtb_miss_single";
67FaultVect NDtbMissFault::_vect = 0x0201;
68FaultStat NDtbMissFault::_count;
69
70FaultName PDtbMissFault::_name = "dtb_miss_double";
71FaultVect PDtbMissFault::_vect = 0x0281;
72FaultStat PDtbMissFault::_count;
73
74FaultName DtbPageFault::_name = "dfault";
75FaultVect DtbPageFault::_vect = 0x0381;
76FaultStat DtbPageFault::_count;
77
78FaultName DtbAcvFault::_name = "dfault";
79FaultVect DtbAcvFault::_vect = 0x0381;
80FaultStat DtbAcvFault::_count;
81
82FaultName DtbAlignmentFault::_name = "unalign";
83FaultVect DtbAlignmentFault::_vect = 0x0301;
84FaultStat DtbAlignmentFault::_count;
85
86FaultName ItbPageFault::_name = "itbmiss";
87FaultVect ItbPageFault::_vect = 0x0181;
88FaultStat ItbPageFault::_count;
89
90FaultName ItbAcvFault::_name = "iaccvio";
91FaultVect ItbAcvFault::_vect = 0x0081;
92FaultStat ItbAcvFault::_count;
93
94FaultName UnimplementedOpcodeFault::_name = "opdec";
95FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
96FaultStat UnimplementedOpcodeFault::_count;
97
98FaultName FloatEnableFault::_name = "fen";
99FaultVect FloatEnableFault::_vect = 0x0581;
100FaultStat FloatEnableFault::_count;
101
102FaultName PalFault::_name = "pal";
103FaultVect PalFault::_vect = 0x2001;
104FaultStat PalFault::_count;
105
106FaultName IntegerOverflowFault::_name = "intover";
107FaultVect IntegerOverflowFault::_vect = 0x0501;
108FaultStat IntegerOverflowFault::_count;
109
110#if FULL_SYSTEM
111
| 44
45FaultName MachineCheckFault::_name = "mchk";
46FaultVect MachineCheckFault::_vect = 0x0401;
47FaultStat MachineCheckFault::_count;
48
49FaultName AlignmentFault::_name = "unalign";
50FaultVect AlignmentFault::_vect = 0x0301;
51FaultStat AlignmentFault::_count;
52
53FaultName ResetFault::_name = "reset";
54FaultVect ResetFault::_vect = 0x0001;
55FaultStat ResetFault::_count;
56
57FaultName ArithmeticFault::_name = "arith";
58FaultVect ArithmeticFault::_vect = 0x0501;
59FaultStat ArithmeticFault::_count;
60
61FaultName InterruptFault::_name = "interrupt";
62FaultVect InterruptFault::_vect = 0x0101;
63FaultStat InterruptFault::_count;
64
65FaultName NDtbMissFault::_name = "dtb_miss_single";
66FaultVect NDtbMissFault::_vect = 0x0201;
67FaultStat NDtbMissFault::_count;
68
69FaultName PDtbMissFault::_name = "dtb_miss_double";
70FaultVect PDtbMissFault::_vect = 0x0281;
71FaultStat PDtbMissFault::_count;
72
73FaultName DtbPageFault::_name = "dfault";
74FaultVect DtbPageFault::_vect = 0x0381;
75FaultStat DtbPageFault::_count;
76
77FaultName DtbAcvFault::_name = "dfault";
78FaultVect DtbAcvFault::_vect = 0x0381;
79FaultStat DtbAcvFault::_count;
80
81FaultName DtbAlignmentFault::_name = "unalign";
82FaultVect DtbAlignmentFault::_vect = 0x0301;
83FaultStat DtbAlignmentFault::_count;
84
85FaultName ItbPageFault::_name = "itbmiss";
86FaultVect ItbPageFault::_vect = 0x0181;
87FaultStat ItbPageFault::_count;
88
89FaultName ItbAcvFault::_name = "iaccvio";
90FaultVect ItbAcvFault::_vect = 0x0081;
91FaultStat ItbAcvFault::_count;
92
93FaultName UnimplementedOpcodeFault::_name = "opdec";
94FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
95FaultStat UnimplementedOpcodeFault::_count;
96
97FaultName FloatEnableFault::_name = "fen";
98FaultVect FloatEnableFault::_vect = 0x0581;
99FaultStat FloatEnableFault::_count;
100
101FaultName PalFault::_name = "pal";
102FaultVect PalFault::_vect = 0x2001;
103FaultStat PalFault::_count;
104
105FaultName IntegerOverflowFault::_name = "intover";
106FaultVect IntegerOverflowFault::_vect = 0x0501;
107FaultStat IntegerOverflowFault::_count;
108
109#if FULL_SYSTEM
110
|
112void AlphaFault::invoke(ThreadContext * tc)
| 111void
112AlphaFault::invoke(ThreadContext *tc)
|
113{
114 FaultBase::invoke(tc);
115 countStat()++;
116
117 // exception restart address
118 if (setRestartAddress() || !(tc->readPC() & 0x3))
119 tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC());
120
121 if (skipFaultingInstruction()) {
122 // traps... skip faulting instruction.
123 tc->setMiscRegNoEffect(IPR_EXC_ADDR,
124 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
125 }
126
127 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
128 tc->setNextPC(tc->readPC() + sizeof(MachInst));
129}
130
| 113{
114 FaultBase::invoke(tc);
115 countStat()++;
116
117 // exception restart address
118 if (setRestartAddress() || !(tc->readPC() & 0x3))
119 tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC());
120
121 if (skipFaultingInstruction()) {
122 // traps... skip faulting instruction.
123 tc->setMiscRegNoEffect(IPR_EXC_ADDR,
124 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
125 }
126
127 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
128 tc->setNextPC(tc->readPC() + sizeof(MachInst));
129}
130
|
131void ArithmeticFault::invoke(ThreadContext * tc)
| 131void
132ArithmeticFault::invoke(ThreadContext *tc)
|
132{
133 FaultBase::invoke(tc);
134 panic("Arithmetic traps are unimplemented!");
135}
136
| 133{
134 FaultBase::invoke(tc);
135 panic("Arithmetic traps are unimplemented!");
136}
137
|
137void DtbFault::invoke(ThreadContext * tc)
| 138void
139DtbFault::invoke(ThreadContext *tc)
|
138{
139 // Set fault address and flags. Even though we're modeling an
140 // EV5, we use the EV6 technique of not latching fault registers
141 // on VPTE loads (instead of locking the registers until IPR_VA is
142 // read, like the EV5). The EV6 approach is cleaner and seems to
143 // work with EV5 PAL code, but not the other way around.
| 140{
141 // Set fault address and flags. Even though we're modeling an
142 // EV5, we use the EV6 technique of not latching fault registers
143 // on VPTE loads (instead of locking the registers until IPR_VA is
144 // read, like the EV5). The EV6 approach is cleaner and seems to
145 // work with EV5 PAL code, but not the other way around.
|
144 if (!tc->misspeculating()
145 && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
| 146 if (!tc->misspeculating() &&
147 !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
|
146 // set VA register with faulting address
147 tc->setMiscRegNoEffect(IPR_VA, vaddr);
148
149 // set MM_STAT register flags
150 tc->setMiscRegNoEffect(IPR_MM_STAT,
| 148 // set VA register with faulting address
149 tc->setMiscRegNoEffect(IPR_VA, vaddr);
150
151 // set MM_STAT register flags
152 tc->setMiscRegNoEffect(IPR_MM_STAT,
|
151 (((Opcode(tc->getInst()) & 0x3f) << 11)
152 | ((Ra(tc->getInst()) & 0x1f) << 6)
153 | (flags & 0x3f)));
| 153 (((Opcode(tc->getInst()) & 0x3f) << 11) |
154 ((Ra(tc->getInst()) & 0x1f) << 6) |
155 (flags & 0x3f)));
|
154
155 // set VA_FORM register with faulting formatted address
156 tc->setMiscRegNoEffect(IPR_VA_FORM,
157 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
158 }
159
160 AlphaFault::invoke(tc);
161}
162
| 156
157 // set VA_FORM register with faulting formatted address
158 tc->setMiscRegNoEffect(IPR_VA_FORM,
159 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
160 }
161
162 AlphaFault::invoke(tc);
163}
164
|
163void ItbFault::invoke(ThreadContext * tc)
| 165void
166ItbFault::invoke(ThreadContext *tc)
|
164{
165 if (!tc->misspeculating()) {
166 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
167 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
| 167{
168 if (!tc->misspeculating()) {
169 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
170 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
|
168 tc->readMiscRegNoEffect(IPR_IVPTBR) |
169 (VAddr(pc).vpn() << 3));
| 171 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
|
170 }
171
172 AlphaFault::invoke(tc);
173}
174
175#else
176
| 172 }
173
174 AlphaFault::invoke(tc);
175}
176
177#else
178
|
177void ItbPageFault::invoke(ThreadContext * tc)
| 179void
180ItbPageFault::invoke(ThreadContext *tc)
|
178{
179 Process *p = tc->getProcessPtr();
180 TlbEntry entry;
181 bool success = p->pTable->lookup(pc, entry);
| 181{
182 Process *p = tc->getProcessPtr();
183 TlbEntry entry;
184 bool success = p->pTable->lookup(pc, entry);
|
182 if(!success) {
| 185 if (!success) {
|
183 panic("Tried to execute unmapped address %#x.\n", pc);
184 } else {
185 VAddr vaddr(pc);
186 tc->getITBPtr()->insert(vaddr.page(), entry);
187 }
188}
189
| 186 panic("Tried to execute unmapped address %#x.\n", pc);
187 } else {
188 VAddr vaddr(pc);
189 tc->getITBPtr()->insert(vaddr.page(), entry);
190 }
191}
192
|
190void NDtbMissFault::invoke(ThreadContext * tc)
| 193void
194NDtbMissFault::invoke(ThreadContext *tc)
|
191{
192 Process *p = tc->getProcessPtr();
193 TlbEntry entry;
194 bool success = p->pTable->lookup(vaddr, entry);
| 195{
196 Process *p = tc->getProcessPtr();
197 TlbEntry entry;
198 bool success = p->pTable->lookup(vaddr, entry);
|
195 if(!success) {
| 199 if (!success) {
|
196 p->checkAndAllocNextPage(vaddr);
197 success = p->pTable->lookup(vaddr, entry);
198 }
| 200 p->checkAndAllocNextPage(vaddr);
201 success = p->pTable->lookup(vaddr, entry);
202 }
|
199 if(!success) {
| 203 if (!success) {
|
200 panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
201 } else {
202 tc->getDTBPtr()->insert(vaddr.page(), entry);
203 }
204}
205
206#endif
207
208} // namespace AlphaISA
209
| 204 panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
205 } else {
206 tc->getDTBPtr()->insert(vaddr.page(), entry);
207 }
208}
209
210#endif
211
212} // namespace AlphaISA
213
|