faults.cc (4997:e7380529bd2d) faults.cc (5004:7d94cedab264)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include "arch/alpha/ev5.hh"
33#include "arch/alpha/faults.hh"
34#include "arch/alpha/tlb.hh"
35#include "cpu/thread_context.hh"
36#include "cpu/base.hh"
37#include "base/trace.hh"
38#if !FULL_SYSTEM
39#include "sim/process.hh"
40#include "mem/page_table.hh"
41#endif
42
43namespace AlphaISA
44{
45
46FaultName MachineCheckFault::_name = "mchk";
47FaultVect MachineCheckFault::_vect = 0x0401;
48FaultStat MachineCheckFault::_count;
49
50FaultName AlignmentFault::_name = "unalign";
51FaultVect AlignmentFault::_vect = 0x0301;
52FaultStat AlignmentFault::_count;
53
54FaultName ResetFault::_name = "reset";
55FaultVect ResetFault::_vect = 0x0001;
56FaultStat ResetFault::_count;
57
58FaultName ArithmeticFault::_name = "arith";
59FaultVect ArithmeticFault::_vect = 0x0501;
60FaultStat ArithmeticFault::_count;
61
62FaultName InterruptFault::_name = "interrupt";
63FaultVect InterruptFault::_vect = 0x0101;
64FaultStat InterruptFault::_count;
65
66FaultName NDtbMissFault::_name = "dtb_miss_single";
67FaultVect NDtbMissFault::_vect = 0x0201;
68FaultStat NDtbMissFault::_count;
69
70FaultName PDtbMissFault::_name = "dtb_miss_double";
71FaultVect PDtbMissFault::_vect = 0x0281;
72FaultStat PDtbMissFault::_count;
73
74FaultName DtbPageFault::_name = "dfault";
75FaultVect DtbPageFault::_vect = 0x0381;
76FaultStat DtbPageFault::_count;
77
78FaultName DtbAcvFault::_name = "dfault";
79FaultVect DtbAcvFault::_vect = 0x0381;
80FaultStat DtbAcvFault::_count;
81
82FaultName DtbAlignmentFault::_name = "unalign";
83FaultVect DtbAlignmentFault::_vect = 0x0301;
84FaultStat DtbAlignmentFault::_count;
85
86FaultName ItbPageFault::_name = "itbmiss";
87FaultVect ItbPageFault::_vect = 0x0181;
88FaultStat ItbPageFault::_count;
89
90FaultName ItbAcvFault::_name = "iaccvio";
91FaultVect ItbAcvFault::_vect = 0x0081;
92FaultStat ItbAcvFault::_count;
93
94FaultName UnimplementedOpcodeFault::_name = "opdec";
95FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
96FaultStat UnimplementedOpcodeFault::_count;
97
98FaultName FloatEnableFault::_name = "fen";
99FaultVect FloatEnableFault::_vect = 0x0581;
100FaultStat FloatEnableFault::_count;
101
102FaultName PalFault::_name = "pal";
103FaultVect PalFault::_vect = 0x2001;
104FaultStat PalFault::_count;
105
106FaultName IntegerOverflowFault::_name = "intover";
107FaultVect IntegerOverflowFault::_vect = 0x0501;
108FaultStat IntegerOverflowFault::_count;
109
110#if FULL_SYSTEM
111
112void AlphaFault::invoke(ThreadContext * tc)
113{
114 FaultBase::invoke(tc);
115 countStat()++;
116
117 // exception restart address
118 if (setRestartAddress() || !(tc->readPC() & 0x3))
119 tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC());
120
121 if (skipFaultingInstruction()) {
122 // traps... skip faulting instruction.
123 tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
124 tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4);
125 }
126
127 tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect());
128 tc->setNextPC(tc->readPC() + sizeof(MachInst));
129}
130
131void ArithmeticFault::invoke(ThreadContext * tc)
132{
133 FaultBase::invoke(tc);
134 panic("Arithmetic traps are unimplemented!");
135}
136
137void DtbFault::invoke(ThreadContext * tc)
138{
139 // Set fault address and flags. Even though we're modeling an
140 // EV5, we use the EV6 technique of not latching fault registers
141 // on VPTE loads (instead of locking the registers until IPR_VA is
142 // read, like the EV5). The EV6 approach is cleaner and seems to
143 // work with EV5 PAL code, but not the other way around.
144 if (!tc->misspeculating()
145 && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
146 // set VA register with faulting address
147 tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr);
148
149 // set MM_STAT register flags
150 tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
151 (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
152 | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
153 | (flags & 0x3f)));
154
155 // set VA_FORM register with faulting formatted address
156 tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM,
157 tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
158 }
159
160 AlphaFault::invoke(tc);
161}
162
163void ItbFault::invoke(ThreadContext * tc)
164{
165 if (!tc->misspeculating()) {
166 tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc);
167 tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM,
168 tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) |
169 (AlphaISA::VAddr(pc).vpn() << 3));
170 }
171
172 AlphaFault::invoke(tc);
173}
174
175#else
176
177void ItbPageFault::invoke(ThreadContext * tc)
178{
179 Process *p = tc->getProcessPtr();
180 Addr physaddr;
181 bool success = p->pTable->translate(pc, physaddr);
182 if(!success) {
183 panic("Tried to execute unmapped address %#x.\n", pc);
184 } else {
185 VAddr vaddr(pc);
186 VAddr paddr(physaddr);
187
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include "arch/alpha/ev5.hh"
33#include "arch/alpha/faults.hh"
34#include "arch/alpha/tlb.hh"
35#include "cpu/thread_context.hh"
36#include "cpu/base.hh"
37#include "base/trace.hh"
38#if !FULL_SYSTEM
39#include "sim/process.hh"
40#include "mem/page_table.hh"
41#endif
42
43namespace AlphaISA
44{
45
46FaultName MachineCheckFault::_name = "mchk";
47FaultVect MachineCheckFault::_vect = 0x0401;
48FaultStat MachineCheckFault::_count;
49
50FaultName AlignmentFault::_name = "unalign";
51FaultVect AlignmentFault::_vect = 0x0301;
52FaultStat AlignmentFault::_count;
53
54FaultName ResetFault::_name = "reset";
55FaultVect ResetFault::_vect = 0x0001;
56FaultStat ResetFault::_count;
57
58FaultName ArithmeticFault::_name = "arith";
59FaultVect ArithmeticFault::_vect = 0x0501;
60FaultStat ArithmeticFault::_count;
61
62FaultName InterruptFault::_name = "interrupt";
63FaultVect InterruptFault::_vect = 0x0101;
64FaultStat InterruptFault::_count;
65
66FaultName NDtbMissFault::_name = "dtb_miss_single";
67FaultVect NDtbMissFault::_vect = 0x0201;
68FaultStat NDtbMissFault::_count;
69
70FaultName PDtbMissFault::_name = "dtb_miss_double";
71FaultVect PDtbMissFault::_vect = 0x0281;
72FaultStat PDtbMissFault::_count;
73
74FaultName DtbPageFault::_name = "dfault";
75FaultVect DtbPageFault::_vect = 0x0381;
76FaultStat DtbPageFault::_count;
77
78FaultName DtbAcvFault::_name = "dfault";
79FaultVect DtbAcvFault::_vect = 0x0381;
80FaultStat DtbAcvFault::_count;
81
82FaultName DtbAlignmentFault::_name = "unalign";
83FaultVect DtbAlignmentFault::_vect = 0x0301;
84FaultStat DtbAlignmentFault::_count;
85
86FaultName ItbPageFault::_name = "itbmiss";
87FaultVect ItbPageFault::_vect = 0x0181;
88FaultStat ItbPageFault::_count;
89
90FaultName ItbAcvFault::_name = "iaccvio";
91FaultVect ItbAcvFault::_vect = 0x0081;
92FaultStat ItbAcvFault::_count;
93
94FaultName UnimplementedOpcodeFault::_name = "opdec";
95FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
96FaultStat UnimplementedOpcodeFault::_count;
97
98FaultName FloatEnableFault::_name = "fen";
99FaultVect FloatEnableFault::_vect = 0x0581;
100FaultStat FloatEnableFault::_count;
101
102FaultName PalFault::_name = "pal";
103FaultVect PalFault::_vect = 0x2001;
104FaultStat PalFault::_count;
105
106FaultName IntegerOverflowFault::_name = "intover";
107FaultVect IntegerOverflowFault::_vect = 0x0501;
108FaultStat IntegerOverflowFault::_count;
109
110#if FULL_SYSTEM
111
112void AlphaFault::invoke(ThreadContext * tc)
113{
114 FaultBase::invoke(tc);
115 countStat()++;
116
117 // exception restart address
118 if (setRestartAddress() || !(tc->readPC() & 0x3))
119 tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC());
120
121 if (skipFaultingInstruction()) {
122 // traps... skip faulting instruction.
123 tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
124 tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4);
125 }
126
127 tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect());
128 tc->setNextPC(tc->readPC() + sizeof(MachInst));
129}
130
131void ArithmeticFault::invoke(ThreadContext * tc)
132{
133 FaultBase::invoke(tc);
134 panic("Arithmetic traps are unimplemented!");
135}
136
137void DtbFault::invoke(ThreadContext * tc)
138{
139 // Set fault address and flags. Even though we're modeling an
140 // EV5, we use the EV6 technique of not latching fault registers
141 // on VPTE loads (instead of locking the registers until IPR_VA is
142 // read, like the EV5). The EV6 approach is cleaner and seems to
143 // work with EV5 PAL code, but not the other way around.
144 if (!tc->misspeculating()
145 && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
146 // set VA register with faulting address
147 tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr);
148
149 // set MM_STAT register flags
150 tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
151 (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
152 | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
153 | (flags & 0x3f)));
154
155 // set VA_FORM register with faulting formatted address
156 tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM,
157 tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
158 }
159
160 AlphaFault::invoke(tc);
161}
162
163void ItbFault::invoke(ThreadContext * tc)
164{
165 if (!tc->misspeculating()) {
166 tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc);
167 tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM,
168 tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) |
169 (AlphaISA::VAddr(pc).vpn() << 3));
170 }
171
172 AlphaFault::invoke(tc);
173}
174
175#else
176
177void ItbPageFault::invoke(ThreadContext * tc)
178{
179 Process *p = tc->getProcessPtr();
180 Addr physaddr;
181 bool success = p->pTable->translate(pc, physaddr);
182 if(!success) {
183 panic("Tried to execute unmapped address %#x.\n", pc);
184 } else {
185 VAddr vaddr(pc);
186 VAddr paddr(physaddr);
187
188 PTE pte;
189 pte.tag = vaddr.vpn();
190 pte.ppn = paddr.vpn();
191 pte.xre = 15; //This can be read in all modes.
192 pte.xwe = 1; //This can be written only in kernel mode.
193 pte.asn = p->M5_pid; //Address space number.
194 pte.asma = false; //Only match on this ASN.
195 pte.fonr = false; //Don't fault on read.
196 pte.fonw = false; //Don't fault on write.
197 pte.valid = true; //This entry is valid.
188 TlbEntry entry;
189 entry.tag = vaddr.vpn();
190 entry.ppn = paddr.vpn();
191 entry.xre = 15; //This can be read in all modes.
192 entry.xwe = 1; //This can be written only in kernel mode.
193 entry.asn = p->M5_pid; //Address space number.
194 entry.asma = false; //Only match on this ASN.
195 entry.fonr = false; //Don't fault on read.
196 entry.fonw = false; //Don't fault on write.
197 entry.valid = true; //This entry is valid.
198
198
199 tc->getITBPtr()->insert(vaddr.page(), pte);
199 tc->getITBPtr()->insert(vaddr.page(), entry);
200 }
201}
202
203void NDtbMissFault::invoke(ThreadContext * tc)
204{
205 Process *p = tc->getProcessPtr();
206 Addr physaddr;
207 bool success = p->pTable->translate(vaddr, physaddr);
208 if(!success) {
209 p->checkAndAllocNextPage(vaddr);
210 success = p->pTable->translate(vaddr, physaddr);
211 }
212 if(!success) {
213 panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
214 } else {
215 VAddr paddr(physaddr);
216
200 }
201}
202
203void NDtbMissFault::invoke(ThreadContext * tc)
204{
205 Process *p = tc->getProcessPtr();
206 Addr physaddr;
207 bool success = p->pTable->translate(vaddr, physaddr);
208 if(!success) {
209 p->checkAndAllocNextPage(vaddr);
210 success = p->pTable->translate(vaddr, physaddr);
211 }
212 if(!success) {
213 panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
214 } else {
215 VAddr paddr(physaddr);
216
217 PTE pte;
218 pte.tag = vaddr.vpn();
219 pte.ppn = paddr.vpn();
220 pte.xre = 15; //This can be read in all modes.
221 pte.xwe = 15; //This can be written in all modes.
222 pte.asn = p->M5_pid; //Address space number.
223 pte.asma = false; //Only match on this ASN.
224 pte.fonr = false; //Don't fault on read.
225 pte.fonw = false; //Don't fault on write.
226 pte.valid = true; //This entry is valid.
217 TlbEntry entry;
218 entry.tag = vaddr.vpn();
219 entry.ppn = paddr.vpn();
220 entry.xre = 15; //This can be read in all modes.
221 entry.xwe = 15; //This can be written in all modes.
222 entry.asn = p->M5_pid; //Address space number.
223 entry.asma = false; //Only match on this ASN.
224 entry.fonr = false; //Don't fault on read.
225 entry.fonw = false; //Don't fault on write.
226 entry.valid = true; //This entry is valid.
227
227
228 tc->getDTBPtr()->insert(vaddr.page(), pte);
228 tc->getDTBPtr()->insert(vaddr.page(), entry);
229 }
230}
231
232#endif
233
234} // namespace AlphaISA
235
229 }
230}
231
232#endif
233
234} // namespace AlphaISA
235