1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Kevin Lim 30 */ 31 32#include "arch/alpha/faults.hh"
| 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Kevin Lim 30 */ 31 32#include "arch/alpha/faults.hh"
|
33#include "cpu/exec_context.hh"
| 33#include "cpu/thread_context.hh"
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34#include "cpu/base.hh" 35#include "base/trace.hh" 36#if FULL_SYSTEM 37#include "arch/alpha/ev5.hh" 38#endif 39 40namespace AlphaISA 41{ 42 43FaultName MachineCheckFault::_name = "mchk"; 44FaultVect MachineCheckFault::_vect = 0x0401; 45FaultStat MachineCheckFault::_count; 46 47FaultName AlignmentFault::_name = "unalign"; 48FaultVect AlignmentFault::_vect = 0x0301; 49FaultStat AlignmentFault::_count; 50 51FaultName ResetFault::_name = "reset"; 52FaultVect ResetFault::_vect = 0x0001; 53FaultStat ResetFault::_count; 54 55FaultName ArithmeticFault::_name = "arith"; 56FaultVect ArithmeticFault::_vect = 0x0501; 57FaultStat ArithmeticFault::_count; 58 59FaultName InterruptFault::_name = "interrupt"; 60FaultVect InterruptFault::_vect = 0x0101; 61FaultStat InterruptFault::_count; 62 63FaultName NDtbMissFault::_name = "dtb_miss_single"; 64FaultVect NDtbMissFault::_vect = 0x0201; 65FaultStat NDtbMissFault::_count; 66 67FaultName PDtbMissFault::_name = "dtb_miss_double"; 68FaultVect PDtbMissFault::_vect = 0x0281; 69FaultStat PDtbMissFault::_count; 70 71FaultName DtbPageFault::_name = "dfault"; 72FaultVect DtbPageFault::_vect = 0x0381; 73FaultStat DtbPageFault::_count; 74 75FaultName DtbAcvFault::_name = "dfault"; 76FaultVect DtbAcvFault::_vect = 0x0381; 77FaultStat DtbAcvFault::_count; 78 79FaultName DtbAlignmentFault::_name = "unalign"; 80FaultVect DtbAlignmentFault::_vect = 0x0301; 81FaultStat DtbAlignmentFault::_count; 82 83FaultName ItbMissFault::_name = "itbmiss"; 84FaultVect ItbMissFault::_vect = 0x0181; 85FaultStat ItbMissFault::_count; 86 87FaultName ItbPageFault::_name = "itbmiss"; 88FaultVect ItbPageFault::_vect = 0x0181; 89FaultStat ItbPageFault::_count; 90 91FaultName ItbAcvFault::_name = "iaccvio"; 92FaultVect ItbAcvFault::_vect = 0x0081; 93FaultStat ItbAcvFault::_count; 94 95FaultName UnimplementedOpcodeFault::_name = "opdec"; 96FaultVect UnimplementedOpcodeFault::_vect = 0x0481; 97FaultStat UnimplementedOpcodeFault::_count; 98 99FaultName FloatEnableFault::_name = "fen"; 100FaultVect FloatEnableFault::_vect = 0x0581; 101FaultStat FloatEnableFault::_count; 102 103FaultName PalFault::_name = "pal"; 104FaultVect PalFault::_vect = 0x2001; 105FaultStat PalFault::_count; 106 107FaultName IntegerOverflowFault::_name = "intover"; 108FaultVect IntegerOverflowFault::_vect = 0x0501; 109FaultStat IntegerOverflowFault::_count; 110 111#if FULL_SYSTEM 112
| 34#include "cpu/base.hh" 35#include "base/trace.hh" 36#if FULL_SYSTEM 37#include "arch/alpha/ev5.hh" 38#endif 39 40namespace AlphaISA 41{ 42 43FaultName MachineCheckFault::_name = "mchk"; 44FaultVect MachineCheckFault::_vect = 0x0401; 45FaultStat MachineCheckFault::_count; 46 47FaultName AlignmentFault::_name = "unalign"; 48FaultVect AlignmentFault::_vect = 0x0301; 49FaultStat AlignmentFault::_count; 50 51FaultName ResetFault::_name = "reset"; 52FaultVect ResetFault::_vect = 0x0001; 53FaultStat ResetFault::_count; 54 55FaultName ArithmeticFault::_name = "arith"; 56FaultVect ArithmeticFault::_vect = 0x0501; 57FaultStat ArithmeticFault::_count; 58 59FaultName InterruptFault::_name = "interrupt"; 60FaultVect InterruptFault::_vect = 0x0101; 61FaultStat InterruptFault::_count; 62 63FaultName NDtbMissFault::_name = "dtb_miss_single"; 64FaultVect NDtbMissFault::_vect = 0x0201; 65FaultStat NDtbMissFault::_count; 66 67FaultName PDtbMissFault::_name = "dtb_miss_double"; 68FaultVect PDtbMissFault::_vect = 0x0281; 69FaultStat PDtbMissFault::_count; 70 71FaultName DtbPageFault::_name = "dfault"; 72FaultVect DtbPageFault::_vect = 0x0381; 73FaultStat DtbPageFault::_count; 74 75FaultName DtbAcvFault::_name = "dfault"; 76FaultVect DtbAcvFault::_vect = 0x0381; 77FaultStat DtbAcvFault::_count; 78 79FaultName DtbAlignmentFault::_name = "unalign"; 80FaultVect DtbAlignmentFault::_vect = 0x0301; 81FaultStat DtbAlignmentFault::_count; 82 83FaultName ItbMissFault::_name = "itbmiss"; 84FaultVect ItbMissFault::_vect = 0x0181; 85FaultStat ItbMissFault::_count; 86 87FaultName ItbPageFault::_name = "itbmiss"; 88FaultVect ItbPageFault::_vect = 0x0181; 89FaultStat ItbPageFault::_count; 90 91FaultName ItbAcvFault::_name = "iaccvio"; 92FaultVect ItbAcvFault::_vect = 0x0081; 93FaultStat ItbAcvFault::_count; 94 95FaultName UnimplementedOpcodeFault::_name = "opdec"; 96FaultVect UnimplementedOpcodeFault::_vect = 0x0481; 97FaultStat UnimplementedOpcodeFault::_count; 98 99FaultName FloatEnableFault::_name = "fen"; 100FaultVect FloatEnableFault::_vect = 0x0581; 101FaultStat FloatEnableFault::_count; 102 103FaultName PalFault::_name = "pal"; 104FaultVect PalFault::_vect = 0x2001; 105FaultStat PalFault::_count; 106 107FaultName IntegerOverflowFault::_name = "intover"; 108FaultVect IntegerOverflowFault::_vect = 0x0501; 109FaultStat IntegerOverflowFault::_count; 110 111#if FULL_SYSTEM 112
|
113void AlphaFault::invoke(ExecContext * xc)
| 113void AlphaFault::invoke(ThreadContext * tc)
|
114{
| 114{
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115 FaultBase::invoke(xc);
| 115 FaultBase::invoke(tc);
|
116 countStat()++; 117 118 // exception restart address
| 116 countStat()++; 117 118 // exception restart address
|
119 if (setRestartAddress() || !xc->inPalMode()) 120 xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC());
| 119 if (setRestartAddress() || !tc->inPalMode()) 120 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
|
121 122 if (skipFaultingInstruction()) { 123 // traps... skip faulting instruction.
| 121 122 if (skipFaultingInstruction()) { 123 // traps... skip faulting instruction.
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124 xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, 125 xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
| 124 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, 125 tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
|
126 } 127
| 126 } 127
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128 xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect()); 129 xc->setNextPC(xc->readPC() + sizeof(MachInst));
| 128 tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect()); 129 tc->setNextPC(tc->readPC() + sizeof(MachInst));
|
130} 131
| 130} 131
|
132void ArithmeticFault::invoke(ExecContext * xc)
| 132void ArithmeticFault::invoke(ThreadContext * tc)
|
133{
| 133{
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134 FaultBase::invoke(xc);
| 134 FaultBase::invoke(tc);
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135 panic("Arithmetic traps are unimplemented!"); 136} 137
| 135 panic("Arithmetic traps are unimplemented!"); 136} 137
|
138void DtbFault::invoke(ExecContext * xc)
| 138void DtbFault::invoke(ThreadContext * tc)
|
139{ 140 // Set fault address and flags. Even though we're modeling an 141 // EV5, we use the EV6 technique of not latching fault registers 142 // on VPTE loads (instead of locking the registers until IPR_VA is 143 // read, like the EV5). The EV6 approach is cleaner and seems to 144 // work with EV5 PAL code, but not the other way around.
| 139{ 140 // Set fault address and flags. Even though we're modeling an 141 // EV5, we use the EV6 technique of not latching fault registers 142 // on VPTE loads (instead of locking the registers until IPR_VA is 143 // read, like the EV5). The EV6 approach is cleaner and seems to 144 // work with EV5 PAL code, but not the other way around.
|
145 if (!xc->misspeculating()
| 145 if (!tc->misspeculating()
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146 && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { 147 // set VA register with faulting address
| 146 && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { 147 // set VA register with faulting address
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148 xc->setMiscReg(AlphaISA::IPR_VA, vaddr);
| 148 tc->setMiscReg(AlphaISA::IPR_VA, vaddr);
|
149 150 // set MM_STAT register flags
| 149 150 // set MM_STAT register flags
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151 xc->setMiscReg(AlphaISA::IPR_MM_STAT, 152 (((EV5::Opcode(xc->getInst()) & 0x3f) << 11) 153 | ((EV5::Ra(xc->getInst()) & 0x1f) << 6)
| 151 tc->setMiscReg(AlphaISA::IPR_MM_STAT, 152 (((EV5::Opcode(tc->getInst()) & 0x3f) << 11) 153 | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
|
154 | (flags & 0x3f))); 155 156 // set VA_FORM register with faulting formatted address
| 154 | (flags & 0x3f))); 155 156 // set VA_FORM register with faulting formatted address
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157 xc->setMiscReg(AlphaISA::IPR_VA_FORM, 158 xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
| 157 tc->setMiscReg(AlphaISA::IPR_VA_FORM, 158 tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
|
159 } 160
| 159 } 160
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161 AlphaFault::invoke(xc);
| 161 AlphaFault::invoke(tc);
|
162} 163
| 162} 163
|
164void ItbFault::invoke(ExecContext * xc)
| 164void ItbFault::invoke(ThreadContext * tc)
|
165{
| 165{
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166 if (!xc->misspeculating()) { 167 xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc); 168 xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, 169 xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
| 166 if (!tc->misspeculating()) { 167 tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc); 168 tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, 169 tc->readMiscReg(AlphaISA::IPR_IVPTBR) |
|
170 (AlphaISA::VAddr(pc).vpn() << 3)); 171 } 172
| 170 (AlphaISA::VAddr(pc).vpn() << 3)); 171 } 172
|
173 AlphaFault::invoke(xc);
| 173 AlphaFault::invoke(tc);
|
174} 175 176#endif 177 178} // namespace AlphaISA 179
| 174} 175 176#endif 177 178} // namespace AlphaISA 179
|