1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include "arch/alpha/faults.hh"
33
34#include "arch/alpha/ev5.hh"
35#include "arch/alpha/tlb.hh"
36#include "base/trace.hh"
37#include "cpu/base.hh"
38#include "cpu/thread_context.hh"
39#include "mem/page_table.hh"
40#include "sim/full_system.hh"
41#include "sim/process.hh"
42
43namespace AlphaISA {
44
45FaultName MachineCheckFault::_name = "mchk";
46FaultVect MachineCheckFault::_vect = 0x0401;
47FaultStat MachineCheckFault::_count;
48
49FaultName AlignmentFault::_name = "unalign";
50FaultVect AlignmentFault::_vect = 0x0301;
51FaultStat AlignmentFault::_count;
52
53FaultName ResetFault::_name = "reset";
54FaultVect ResetFault::_vect = 0x0001;
55FaultStat ResetFault::_count;
56
57FaultName ArithmeticFault::_name = "arith";
58FaultVect ArithmeticFault::_vect = 0x0501;
59FaultStat ArithmeticFault::_count;
60
61FaultName InterruptFault::_name = "interrupt";
62FaultVect InterruptFault::_vect = 0x0101;
63FaultStat InterruptFault::_count;
64
65FaultName NDtbMissFault::_name = "dtb_miss_single";
66FaultVect NDtbMissFault::_vect = 0x0201;
67FaultStat NDtbMissFault::_count;
68
69FaultName PDtbMissFault::_name = "dtb_miss_double";
70FaultVect PDtbMissFault::_vect = 0x0281;
71FaultStat PDtbMissFault::_count;
72
73FaultName DtbPageFault::_name = "dtb_page_fault";
74FaultVect DtbPageFault::_vect = 0x0381;
75FaultStat DtbPageFault::_count;
76
77FaultName DtbAcvFault::_name = "dtb_acv_fault";
78FaultVect DtbAcvFault::_vect = 0x0381;
79FaultStat DtbAcvFault::_count;
80
81FaultName DtbAlignmentFault::_name = "unalign";
82FaultVect DtbAlignmentFault::_vect = 0x0301;
83FaultStat DtbAlignmentFault::_count;
84
85FaultName ItbPageFault::_name = "itbmiss";
86FaultVect ItbPageFault::_vect = 0x0181;
87FaultStat ItbPageFault::_count;
88
89FaultName ItbAcvFault::_name = "iaccvio";
90FaultVect ItbAcvFault::_vect = 0x0081;
91FaultStat ItbAcvFault::_count;
92
93FaultName UnimplementedOpcodeFault::_name = "opdec";
94FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
95FaultStat UnimplementedOpcodeFault::_count;
96
97FaultName FloatEnableFault::_name = "fen";
98FaultVect FloatEnableFault::_vect = 0x0581;
99FaultStat FloatEnableFault::_count;
100
101/* We use the same fault vector, as for the guest system these should be the
102 * same, but for host purposes, having differentiation is helpful for
103 * debug/monitorization purposes. */
104FaultName VectorEnableFault::_name = "ven";
105FaultVect VectorEnableFault::_vect = 0x0581;
106FaultStat VectorEnableFault::_count;
107
108FaultName PalFault::_name = "pal";
109FaultVect PalFault::_vect = 0x2001;
110FaultStat PalFault::_count;
111
112FaultName IntegerOverflowFault::_name = "intover";
113FaultVect IntegerOverflowFault::_vect = 0x0501;
114FaultStat IntegerOverflowFault::_count;
115
116void
117AlphaFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
118{
119 FaultBase::invoke(tc);
120 if (!FullSystem)
121 return;
122 countStat()++;
123
124 PCState pc = tc->pcState();
125
126 // exception restart address
127 if (setRestartAddress() || !(pc.pc() & 0x3))
128 tc->setMiscRegNoEffect(IPR_EXC_ADDR, pc.pc());
129
130 if (skipFaultingInstruction()) {
131 // traps... skip faulting instruction.
132 tc->setMiscRegNoEffect(IPR_EXC_ADDR,
133 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
134 }
135
136 pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
137 tc->pcState(pc);
138}
139
140void
141ArithmeticFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
142{
143 FaultBase::invoke(tc);
144 if (!FullSystem)
145 return;
146 panic("Arithmetic traps are unimplemented!");
147}
148
149void
150DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
151{
152 if (FullSystem) {
153 // Set fault address and flags. Even though we're modeling an
154 // EV5, we use the EV6 technique of not latching fault registers
155 // on VPTE loads (instead of locking the registers until IPR_VA is
156 // read, like the EV5). The EV6 approach is cleaner and seems to
157 // work with EV5 PAL code, but not the other way around.
158 if (reqFlags.noneSet(AlphaRequestFlags::VPTE | Request::PREFETCH)) {
159 // set VA register with faulting address
160 tc->setMiscRegNoEffect(IPR_VA, vaddr);
161
162 // set MM_STAT register flags
163 MachInst machInst = inst->machInst;
164 tc->setMiscRegNoEffect(IPR_MM_STAT,
165 (((Opcode(machInst) & 0x3f) << 11) |
166 ((Ra(machInst) & 0x1f) << 6) |
167 (flags & 0x3f)));
168
169 // set VA_FORM register with faulting formatted address
170 tc->setMiscRegNoEffect(IPR_VA_FORM,
171 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
172 }
173 }
174
175 AlphaFault::invoke(tc);
176}
177
178void
179ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
180{
181 if (FullSystem) {
182 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
183 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
184 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
185 }
186
187 AlphaFault::invoke(tc);
188}
189
190void
191ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
192{
193 if (FullSystem) {
194 ItbFault::invoke(tc);
195 return;
196 }
197
198 Process *p = tc->getProcessPtr();
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include "arch/alpha/faults.hh"
33
34#include "arch/alpha/ev5.hh"
35#include "arch/alpha/tlb.hh"
36#include "base/trace.hh"
37#include "cpu/base.hh"
38#include "cpu/thread_context.hh"
39#include "mem/page_table.hh"
40#include "sim/full_system.hh"
41#include "sim/process.hh"
42
43namespace AlphaISA {
44
45FaultName MachineCheckFault::_name = "mchk";
46FaultVect MachineCheckFault::_vect = 0x0401;
47FaultStat MachineCheckFault::_count;
48
49FaultName AlignmentFault::_name = "unalign";
50FaultVect AlignmentFault::_vect = 0x0301;
51FaultStat AlignmentFault::_count;
52
53FaultName ResetFault::_name = "reset";
54FaultVect ResetFault::_vect = 0x0001;
55FaultStat ResetFault::_count;
56
57FaultName ArithmeticFault::_name = "arith";
58FaultVect ArithmeticFault::_vect = 0x0501;
59FaultStat ArithmeticFault::_count;
60
61FaultName InterruptFault::_name = "interrupt";
62FaultVect InterruptFault::_vect = 0x0101;
63FaultStat InterruptFault::_count;
64
65FaultName NDtbMissFault::_name = "dtb_miss_single";
66FaultVect NDtbMissFault::_vect = 0x0201;
67FaultStat NDtbMissFault::_count;
68
69FaultName PDtbMissFault::_name = "dtb_miss_double";
70FaultVect PDtbMissFault::_vect = 0x0281;
71FaultStat PDtbMissFault::_count;
72
73FaultName DtbPageFault::_name = "dtb_page_fault";
74FaultVect DtbPageFault::_vect = 0x0381;
75FaultStat DtbPageFault::_count;
76
77FaultName DtbAcvFault::_name = "dtb_acv_fault";
78FaultVect DtbAcvFault::_vect = 0x0381;
79FaultStat DtbAcvFault::_count;
80
81FaultName DtbAlignmentFault::_name = "unalign";
82FaultVect DtbAlignmentFault::_vect = 0x0301;
83FaultStat DtbAlignmentFault::_count;
84
85FaultName ItbPageFault::_name = "itbmiss";
86FaultVect ItbPageFault::_vect = 0x0181;
87FaultStat ItbPageFault::_count;
88
89FaultName ItbAcvFault::_name = "iaccvio";
90FaultVect ItbAcvFault::_vect = 0x0081;
91FaultStat ItbAcvFault::_count;
92
93FaultName UnimplementedOpcodeFault::_name = "opdec";
94FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
95FaultStat UnimplementedOpcodeFault::_count;
96
97FaultName FloatEnableFault::_name = "fen";
98FaultVect FloatEnableFault::_vect = 0x0581;
99FaultStat FloatEnableFault::_count;
100
101/* We use the same fault vector, as for the guest system these should be the
102 * same, but for host purposes, having differentiation is helpful for
103 * debug/monitorization purposes. */
104FaultName VectorEnableFault::_name = "ven";
105FaultVect VectorEnableFault::_vect = 0x0581;
106FaultStat VectorEnableFault::_count;
107
108FaultName PalFault::_name = "pal";
109FaultVect PalFault::_vect = 0x2001;
110FaultStat PalFault::_count;
111
112FaultName IntegerOverflowFault::_name = "intover";
113FaultVect IntegerOverflowFault::_vect = 0x0501;
114FaultStat IntegerOverflowFault::_count;
115
116void
117AlphaFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
118{
119 FaultBase::invoke(tc);
120 if (!FullSystem)
121 return;
122 countStat()++;
123
124 PCState pc = tc->pcState();
125
126 // exception restart address
127 if (setRestartAddress() || !(pc.pc() & 0x3))
128 tc->setMiscRegNoEffect(IPR_EXC_ADDR, pc.pc());
129
130 if (skipFaultingInstruction()) {
131 // traps... skip faulting instruction.
132 tc->setMiscRegNoEffect(IPR_EXC_ADDR,
133 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
134 }
135
136 pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
137 tc->pcState(pc);
138}
139
140void
141ArithmeticFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
142{
143 FaultBase::invoke(tc);
144 if (!FullSystem)
145 return;
146 panic("Arithmetic traps are unimplemented!");
147}
148
149void
150DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
151{
152 if (FullSystem) {
153 // Set fault address and flags. Even though we're modeling an
154 // EV5, we use the EV6 technique of not latching fault registers
155 // on VPTE loads (instead of locking the registers until IPR_VA is
156 // read, like the EV5). The EV6 approach is cleaner and seems to
157 // work with EV5 PAL code, but not the other way around.
158 if (reqFlags.noneSet(AlphaRequestFlags::VPTE | Request::PREFETCH)) {
159 // set VA register with faulting address
160 tc->setMiscRegNoEffect(IPR_VA, vaddr);
161
162 // set MM_STAT register flags
163 MachInst machInst = inst->machInst;
164 tc->setMiscRegNoEffect(IPR_MM_STAT,
165 (((Opcode(machInst) & 0x3f) << 11) |
166 ((Ra(machInst) & 0x1f) << 6) |
167 (flags & 0x3f)));
168
169 // set VA_FORM register with faulting formatted address
170 tc->setMiscRegNoEffect(IPR_VA_FORM,
171 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
172 }
173 }
174
175 AlphaFault::invoke(tc);
176}
177
178void
179ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
180{
181 if (FullSystem) {
182 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
183 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
184 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
185 }
186
187 AlphaFault::invoke(tc);
188}
189
190void
191ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
192{
193 if (FullSystem) {
194 ItbFault::invoke(tc);
195 return;
196 }
197
198 Process *p = tc->getProcessPtr();
|