faults.cc (5569:baeee670d4ce) | faults.cc (5736:426510e758ad) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 130 unchanged lines hidden (view full) --- 139DtbFault::invoke(ThreadContext *tc) 140{ 141 // Set fault address and flags. Even though we're modeling an 142 // EV5, we use the EV6 technique of not latching fault registers 143 // on VPTE loads (instead of locking the registers until IPR_VA is 144 // read, like the EV5). The EV6 approach is cleaner and seems to 145 // work with EV5 PAL code, but not the other way around. 146 if (!tc->misspeculating() && | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 130 unchanged lines hidden (view full) --- 139DtbFault::invoke(ThreadContext *tc) 140{ 141 // Set fault address and flags. Even though we're modeling an 142 // EV5, we use the EV6 technique of not latching fault registers 143 // on VPTE loads (instead of locking the registers until IPR_VA is 144 // read, like the EV5). The EV6 approach is cleaner and seems to 145 // work with EV5 PAL code, but not the other way around. 146 if (!tc->misspeculating() && |
147 !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { | 147 reqFlags.none(Request::VPTE|Request::NO_FAULT)) { |
148 // set VA register with faulting address 149 tc->setMiscRegNoEffect(IPR_VA, vaddr); 150 151 // set MM_STAT register flags 152 tc->setMiscRegNoEffect(IPR_MM_STAT, 153 (((Opcode(tc->getInst()) & 0x3f) << 11) | 154 ((Ra(tc->getInst()) & 0x1f) << 6) | 155 (flags & 0x3f))); --- 58 unchanged lines hidden --- | 148 // set VA register with faulting address 149 tc->setMiscRegNoEffect(IPR_VA, vaddr); 150 151 // set MM_STAT register flags 152 tc->setMiscRegNoEffect(IPR_MM_STAT, 153 (((Opcode(tc->getInst()) & 0x3f) << 11) | 154 ((Ra(tc->getInst()) & 0x1f) << 6) | 155 (flags & 0x3f))); --- 58 unchanged lines hidden --- |