1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include "arch/alpha/ev5.hh"
33#include "arch/alpha/faults.hh"
34#include "arch/alpha/tlb.hh"
35#include "cpu/thread_context.hh"
36#include "cpu/base.hh"
37#include "base/trace.hh"
38#if !FULL_SYSTEM
39#include "sim/process.hh"
40#include "mem/page_table.hh"
41#endif
42
43namespace AlphaISA
44{
45
46FaultName MachineCheckFault::_name = "mchk";

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78FaultName DtbAcvFault::_name = "dfault";
79FaultVect DtbAcvFault::_vect = 0x0381;
80FaultStat DtbAcvFault::_count;
81
82FaultName DtbAlignmentFault::_name = "unalign";
83FaultVect DtbAlignmentFault::_vect = 0x0301;
84FaultStat DtbAlignmentFault::_count;
85
86FaultName ItbPageFault::_name = "itbmiss";
87FaultVect ItbPageFault::_vect = 0x0181;
88FaultStat ItbPageFault::_count;
89
90FaultName ItbAcvFault::_name = "iaccvio";
91FaultVect ItbAcvFault::_vect = 0x0081;
92FaultStat ItbAcvFault::_count;
93

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167 tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM,
168 tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) |
169 (AlphaISA::VAddr(pc).vpn() << 3));
170 }
171
172 AlphaFault::invoke(tc);
173}
174
175#else
176
177void ItbPageFault::invoke(ThreadContext * tc)
178{
179 Process *p = tc->getProcessPtr();
180 Addr physaddr;
181 bool success = p->pTable->translate(pc, physaddr);
182 if(!success) {
183 panic("Tried to execute unmapped address %#x.\n", pc);
184 } else {
185 VAddr vaddr(pc);
186 VAddr paddr(physaddr);
187
188 PTE pte;
189 pte.tag = vaddr.vpn();
190 pte.ppn = paddr.vpn();
191 pte.xre = 15; //This can be read in all modes.
192 pte.xwe = 1; //This can be written only in kernel mode.
193 pte.asn = p->M5_pid; //Address space number.
194 pte.asma = false; //Only match on this ASN.
195 pte.fonr = false; //Don't fault on read.
196 pte.fonw = false; //Don't fault on write.
197 pte.valid = true; //This entry is valid.
198
199 tc->getITBPtr()->insert(vaddr.page(), pte);
200 }
201}
202
203void NDtbMissFault::invoke(ThreadContext * tc)
204{
205 Process *p = tc->getProcessPtr();
206 Addr physaddr;
207 bool success = p->pTable->translate(vaddr, physaddr);
208 if(!success) {
209 p->checkAndAllocNextPage(vaddr);
210 success = p->pTable->translate(vaddr, physaddr);
211 }
212 if(!success) {
213 panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
214 } else {
215 VAddr paddr(physaddr);
216
217 PTE pte;
218 pte.tag = vaddr.vpn();
219 pte.ppn = paddr.vpn();
220 pte.xre = 15; //This can be read in all modes.
221 pte.xwe = 15; //This can be written in all modes.
222 pte.asn = p->M5_pid; //Address space number.
223 pte.asma = false; //Only match on this ASN.
224 pte.fonr = false; //Don't fault on read.
225 pte.fonw = false; //Don't fault on write.
226 pte.valid = true; //This entry is valid.
227
228 tc->getDTBPtr()->insert(vaddr.page(), pte);
229 }
230}
231
232#endif
233
234} // namespace AlphaISA
235