ev5.cc (8607:5fb918115c07) ev5.cc (8780:89e0822462a1)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 30 unchanged lines hidden (view full) ---

39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
43#include "sim/sim_exit.hh"
44
45namespace AlphaISA {
46
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 30 unchanged lines hidden (view full) ---

39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
43#include "sim/sim_exit.hh"
44
45namespace AlphaISA {
46
47#if FULL_SYSTEM
48
49////////////////////////////////////////////////////////////////////////
50//
51// Machine dependent functions
52//
53void
54initCPU(ThreadContext *tc, int cpuId)
55{
56 initIPRs(tc, cpuId);

--- 14 unchanged lines hidden (view full) ---

71{
72 // Insure ISA semantics
73 // (no longer very clean due to the change in setIntReg() in the
74 // cpu model. Consider changing later.)
75 cpu->thread->setIntReg(ZeroReg, 0);
76 cpu->thread->setFloatReg(ZeroReg, 0.0);
77}
78
47////////////////////////////////////////////////////////////////////////
48//
49// Machine dependent functions
50//
51void
52initCPU(ThreadContext *tc, int cpuId)
53{
54 initIPRs(tc, cpuId);

--- 14 unchanged lines hidden (view full) ---

69{
70 // Insure ISA semantics
71 // (no longer very clean due to the change in setIntReg() in the
72 // cpu model. Consider changing later.)
73 cpu->thread->setIntReg(ZeroReg, 0);
74 cpu->thread->setFloatReg(ZeroReg, 0.0);
75}
76
79#endif
80
81////////////////////////////////////////////////////////////////////////
82//
83//
84//
85void
86initIPRs(ThreadContext *tc, int cpuId)
87{
88 for (int i = 0; i < NumInternalProcRegs; ++i) {

--- 107 unchanged lines hidden (view full) ---

196 // invalid IPR
197 panic("Tried to read from invalid ipr %d\n", idx);
198 break;
199 }
200
201 return retval;
202}
203
77////////////////////////////////////////////////////////////////////////
78//
79//
80//
81void
82initIPRs(ThreadContext *tc, int cpuId)
83{
84 for (int i = 0; i < NumInternalProcRegs; ++i) {

--- 107 unchanged lines hidden (view full) ---

192 // invalid IPR
193 panic("Tried to read from invalid ipr %d\n", idx);
194 break;
195 }
196
197 return retval;
198}
199
204#ifdef DEBUG
205// Cause the simulator to break when changing to the following IPL
206int break_ipl = -1;
200// Cause the simulator to break when changing to the following IPL
201int break_ipl = -1;
207#endif
208
209void
210ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
211{
202
203void
204ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
205{
206 uint64_t old;
207
212 if (tc->misspeculating())
213 return;
214
215 switch (idx) {
216 case IPR_PALtemp0:
217 case IPR_PALtemp1:
218 case IPR_PALtemp2:
219 case IPR_PALtemp3:

--- 35 unchanged lines hidden (view full) ---

255 // This IPR only writes the upper 64 bits. It's ok to write
256 // all 64 here since we mask out the lower 32 in rpcc (see
257 // isa_desc).
258 ipr[idx] = val;
259 break;
260
261 case IPR_PALtemp23:
262 // write entire quad w/ no side-effect
208 if (tc->misspeculating())
209 return;
210
211 switch (idx) {
212 case IPR_PALtemp0:
213 case IPR_PALtemp1:
214 case IPR_PALtemp2:
215 case IPR_PALtemp3:

--- 35 unchanged lines hidden (view full) ---

251 // This IPR only writes the upper 64 bits. It's ok to write
252 // all 64 here since we mask out the lower 32 in rpcc (see
253 // isa_desc).
254 ipr[idx] = val;
255 break;
256
257 case IPR_PALtemp23:
258 // write entire quad w/ no side-effect
263#if FULL_SYSTEM
264 if (tc->getKernelStats())
265 tc->getKernelStats()->context(ipr[idx], val, tc);
266#endif
259 old = ipr[idx];
267 ipr[idx] = val;
260 ipr[idx] = val;
261 if (tc->getKernelStats())
262 tc->getKernelStats()->context(old, val, tc);
268 break;
269
270 case IPR_DTB_PTE:
271 // write entire quad w/ no side-effect, tag is forthcoming
272 ipr[idx] = val;
273 break;
274
275 case IPR_EXC_ADDR:

--- 10 unchanged lines hidden (view full) ---

286 case IPR_IPLR:
287#ifdef DEBUG
288 if (break_ipl != -1 && break_ipl == (int)(val & 0x1f))
289 Debug::breakpoint();
290#endif
291
292 // only write least significant five bits - interrupt level
293 ipr[idx] = val & 0x1f;
263 break;
264
265 case IPR_DTB_PTE:
266 // write entire quad w/ no side-effect, tag is forthcoming
267 ipr[idx] = val;
268 break;
269
270 case IPR_EXC_ADDR:

--- 10 unchanged lines hidden (view full) ---

281 case IPR_IPLR:
282#ifdef DEBUG
283 if (break_ipl != -1 && break_ipl == (int)(val & 0x1f))
284 Debug::breakpoint();
285#endif
286
287 // only write least significant five bits - interrupt level
288 ipr[idx] = val & 0x1f;
294#if FULL_SYSTEM
295 if (tc->getKernelStats())
296 tc->getKernelStats()->swpipl(ipr[idx]);
289 if (tc->getKernelStats())
290 tc->getKernelStats()->swpipl(ipr[idx]);
297#endif
298 break;
299
300 case IPR_DTB_CM:
291 break;
292
293 case IPR_DTB_CM:
301#if FULL_SYSTEM
302 if (val & 0x18) {
303 if (tc->getKernelStats())
304 tc->getKernelStats()->mode(Kernel::user, tc);
305 } else {
306 if (tc->getKernelStats())
307 tc->getKernelStats()->mode(Kernel::kernel, tc);
308 }
294 if (val & 0x18) {
295 if (tc->getKernelStats())
296 tc->getKernelStats()->mode(Kernel::user, tc);
297 } else {
298 if (tc->getKernelStats())
299 tc->getKernelStats()->mode(Kernel::kernel, tc);
300 }
309#endif
310
311 case IPR_ICM:
312 // only write two mode bits - processor mode
313 ipr[idx] = val & 0x18;
314 break;
315
316 case IPR_ALT_MODE:
317 // only write two mode bits - processor mode

--- 160 unchanged lines hidden (view full) ---

478copyIprs(ThreadContext *src, ThreadContext *dest)
479{
480 for (int i = 0; i < NumInternalProcRegs; ++i)
481 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
482}
483
484} // namespace AlphaISA
485
301
302 case IPR_ICM:
303 // only write two mode bits - processor mode
304 ipr[idx] = val & 0x18;
305 break;
306
307 case IPR_ALT_MODE:
308 // only write two mode bits - processor mode

--- 160 unchanged lines hidden (view full) ---

469copyIprs(ThreadContext *src, ThreadContext *dest)
470{
471 for (int i = 0; i < NumInternalProcRegs; ++i)
472 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
473}
474
475} // namespace AlphaISA
476
486#if FULL_SYSTEM
487
488using namespace AlphaISA;
489
490Fault
491SimpleThread::hwrei()
492{
493 PCState pc = pcState();
494 if (!(pc.pc() & 0x3))
495 return new UnimplementedOpcodeFault;

--- 33 unchanged lines hidden (view full) ---

529 case PAL::bugchk:
530 if (system->breakpoint())
531 return false;
532 break;
533 }
534
535 return true;
536}
477using namespace AlphaISA;
478
479Fault
480SimpleThread::hwrei()
481{
482 PCState pc = pcState();
483 if (!(pc.pc() & 0x3))
484 return new UnimplementedOpcodeFault;

--- 33 unchanged lines hidden (view full) ---

518 case PAL::bugchk:
519 if (system->breakpoint())
520 return false;
521 break;
522 }
523
524 return true;
525}
537
538#endif // FULL_SYSTEM