ev5.cc (8231:51cf7f3cf9ac) ev5.cc (8607:5fb918115c07)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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204#ifdef DEBUG
205// Cause the simulator to break when changing to the following IPL
206int break_ipl = -1;
207#endif
208
209void
210ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
211{
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 195 unchanged lines hidden (view full) ---

204#ifdef DEBUG
205// Cause the simulator to break when changing to the following IPL
206int break_ipl = -1;
207#endif
208
209void
210ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
211{
212 uint64_t old;
213
214 if (tc->misspeculating())
215 return;
216
217 switch (idx) {
218 case IPR_PALtemp0:
219 case IPR_PALtemp1:
220 case IPR_PALtemp2:
221 case IPR_PALtemp3:

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257 // This IPR only writes the upper 64 bits. It's ok to write
258 // all 64 here since we mask out the lower 32 in rpcc (see
259 // isa_desc).
260 ipr[idx] = val;
261 break;
262
263 case IPR_PALtemp23:
264 // write entire quad w/ no side-effect
212 if (tc->misspeculating())
213 return;
214
215 switch (idx) {
216 case IPR_PALtemp0:
217 case IPR_PALtemp1:
218 case IPR_PALtemp2:
219 case IPR_PALtemp3:

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255 // This IPR only writes the upper 64 bits. It's ok to write
256 // all 64 here since we mask out the lower 32 in rpcc (see
257 // isa_desc).
258 ipr[idx] = val;
259 break;
260
261 case IPR_PALtemp23:
262 // write entire quad w/ no side-effect
265 old = ipr[idx];
266 ipr[idx] = val;
267#if FULL_SYSTEM
268 if (tc->getKernelStats())
263#if FULL_SYSTEM
264 if (tc->getKernelStats())
269 tc->getKernelStats()->context(old, val, tc);
265 tc->getKernelStats()->context(ipr[idx], val, tc);
270#endif
266#endif
267 ipr[idx] = val;
271 break;
272
273 case IPR_DTB_PTE:
274 // write entire quad w/ no side-effect, tag is forthcoming
275 ipr[idx] = val;
276 break;
277
278 case IPR_EXC_ADDR:

--- 263 unchanged lines hidden --- 		268 break;
269
270 case IPR_DTB_PTE:
271 // write entire quad w/ no side-effect, tag is forthcoming
272 ipr[idx] = val;
273 break;
274
275 case IPR_EXC_ADDR:

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