ev5.cc (6227:a17798f2a52c) ev5.cc (6330:786136379872)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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123 // Insure ISA semantics
124 // (no longer very clean due to the change in setIntReg() in the
125 // cpu model. Consider changing later.)
126 cpu->thread->setIntReg(ZeroReg, 0);
127 cpu->thread->setFloatReg(ZeroReg, 0.0);
128}
129
130int
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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123 // Insure ISA semantics
124 // (no longer very clean due to the change in setIntReg() in the
125 // cpu model. Consider changing later.)
126 cpu->thread->setIntReg(ZeroReg, 0);
127 cpu->thread->setFloatReg(ZeroReg, 0.0);
128}
129
130int
131MiscRegFile::getInstAsid()
131ISA::getInstAsid()
132{
133 return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
134}
135
136int
132{
133 return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
134}
135
136int
137MiscRegFile::getDataAsid()
137ISA::getDataAsid()
138{
139 return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
140}
141
142#endif
143
144////////////////////////////////////////////////////////////////////////
145//

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153 }
154
155 tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
156 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
157 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
158}
159
160MiscReg
138{
139 return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
140}
141
142#endif
143
144////////////////////////////////////////////////////////////////////////
145//

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153 }
154
155 tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
156 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
157 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
158}
159
160MiscReg
161MiscRegFile::readIpr(int idx, ThreadContext *tc)
161ISA::readIpr(int idx, ThreadContext *tc)
162{
163 uint64_t retval = 0; // return value, default 0
164
165 switch (idx) {
166 case IPR_PALtemp0:
167 case IPR_PALtemp1:
168 case IPR_PALtemp2:
169 case IPR_PALtemp3:

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265}
266
267#ifdef DEBUG
268// Cause the simulator to break when changing to the following IPL
269int break_ipl = -1;
270#endif
271
272void
162{
163 uint64_t retval = 0; // return value, default 0
164
165 switch (idx) {
166 case IPR_PALtemp0:
167 case IPR_PALtemp1:
168 case IPR_PALtemp2:
169 case IPR_PALtemp3:

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265}
266
267#ifdef DEBUG
268// Cause the simulator to break when changing to the following IPL
269int break_ipl = -1;
270#endif
271
272void
273MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
273ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
274{
275 uint64_t old;
276
277 if (tc->misspeculating())
278 return;
279
280 switch (idx) {
281 case IPR_PALtemp0:

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275 uint64_t old;
276
277 if (tc->misspeculating())
278 return;
279
280 switch (idx) {
281 case IPR_PALtemp0:

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