ev5.cc (5568:d14250d688d2) ev5.cc (5569:baeee670d4ce)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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454
455 tc->getDTBPtr()->flushProcesses();
456 break;
457
458 case IPR_DTB_IS:
459 // really a control write
460 ipr[idx] = val;
461
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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454
455 tc->getDTBPtr()->flushProcesses();
456 break;
457
458 case IPR_DTB_IS:
459 // really a control write
460 ipr[idx] = val;
461
462 tc->getDTBPtr()->flushAddr(val,
463 DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
462 tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
464 break;
465
466 case IPR_DTB_TAG: {
467 struct TlbEntry entry;
468
469 // FIXME: granularity hints NYI...
470 if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
471 panic("PTE GH field != 0");

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524
525 tc->getITBPtr()->flushProcesses();
526 break;
527
528 case IPR_ITB_IS:
529 // really a control write
530 ipr[idx] = val;
531
463 break;
464
465 case IPR_DTB_TAG: {
466 struct TlbEntry entry;
467
468 // FIXME: granularity hints NYI...
469 if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
470 panic("PTE GH field != 0");

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523
524 tc->getITBPtr()->flushProcesses();
525 break;
526
527 case IPR_ITB_IS:
528 // really a control write
529 ipr[idx] = val;
530
532 tc->getITBPtr()->flushAddr(val,
533 ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
531 tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
534 break;
535
536 default:
537 // invalid IPR
538 panic("Tried to write to invalid ipr %d\n", idx);
539 }
540
541 // no error...
542}
543
532 break;
533
534 default:
535 // invalid IPR
536 panic("Tried to write to invalid ipr %d\n", idx);
537 }
538
539 // no error...
540}
541
544
545void
546copyIprs(ThreadContext *src, ThreadContext *dest)
547{
542void
543copyIprs(ThreadContext *src, ThreadContext *dest)
544{
548 for (int i = 0; i < NumInternalProcRegs; ++i) {
545 for (int i = 0; i < NumInternalProcRegs; ++i)
549 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
546 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
550 }
551}
552
553} // namespace AlphaISA
554
555#if FULL_SYSTEM
547}
548
549} // namespace AlphaISA
550
551#if FULL_SYSTEM
552
556using namespace AlphaISA;
557
558Fault
559SimpleThread::hwrei()
560{
561 if (!(readPC() & 0x3))
562 return new UnimplementedOpcodeFault;
563

--- 39 unchanged lines hidden --- 		553using namespace AlphaISA;
554
555Fault
556SimpleThread::hwrei()
557{
558 if (!(readPC() & 0x3))
559 return new UnimplementedOpcodeFault;
560

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