ev5.cc (5566:3440c9ad49b4) ev5.cc (5567:8fc3b004b0df)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 369 unchanged lines hidden (view full) ---

378 tc->getKernelStats()->swpipl(ipr[idx]);
379#endif
380 break;
381
382 case AlphaISA::IPR_DTB_CM:
383#if FULL_SYSTEM
384 if (val & 0x18) {
385 if (tc->getKernelStats())
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 369 unchanged lines hidden (view full) ---

378 tc->getKernelStats()->swpipl(ipr[idx]);
379#endif
380 break;
381
382 case AlphaISA::IPR_DTB_CM:
383#if FULL_SYSTEM
384 if (val & 0x18) {
385 if (tc->getKernelStats())
386 tc->getKernelStats()->mode(TheISA::Kernel::user, tc);
386 tc->getKernelStats()->mode(AlphaISA::Kernel::user, tc);
387 } else {
388 if (tc->getKernelStats())
387 } else {
388 if (tc->getKernelStats())
389 tc->getKernelStats()->mode(TheISA::Kernel::kernel, tc);
389 tc->getKernelStats()->mode(AlphaISA::Kernel::kernel, tc);
390 }
391#endif
392
393 case AlphaISA::IPR_ICM:
394 // only write two mode bits - processor mode
395 ipr[idx] = val & 0x18;
396 break;
397

--- 202 unchanged lines hidden --- 		390 }
391#endif
392
393 case AlphaISA::IPR_ICM:
394 // only write two mode bits - processor mode
395 ipr[idx] = val & 0x18;
396 break;
397

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