ev5.cc (5543:3af77710f397) ev5.cc (5566:3440c9ad49b4)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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39#include "base/stats/events.hh"
40#include "config/full_system.hh"
41#include "cpu/base.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"
44#include "sim/debug.hh"
45#include "sim/sim_exit.hh"
46
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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39#include "base/stats/events.hh"
40#include "config/full_system.hh"
41#include "cpu/base.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"
44#include "sim/debug.hh"
45#include "sim/sim_exit.hh"
46
47using namespace AlphaISA;
48
47#if FULL_SYSTEM
48
49#if FULL_SYSTEM
50
49using namespace EV5;
50
51////////////////////////////////////////////////////////////////////////
52//
53// Machine dependent functions
54//
55void
56AlphaISA::initCPU(ThreadContext *tc, int cpuId)
57{
58 initIPRs(tc, cpuId);

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141
142 // FIXME: XXX check for interrupts? XXX
143 return NoFault;
144}
145
146int
147AlphaISA::MiscRegFile::getInstAsid()
148{
51////////////////////////////////////////////////////////////////////////
52//
53// Machine dependent functions
54//
55void
56AlphaISA::initCPU(ThreadContext *tc, int cpuId)
57{
58 initIPRs(tc, cpuId);

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141
142 // FIXME: XXX check for interrupts? XXX
143 return NoFault;
144}
145
146int
147AlphaISA::MiscRegFile::getInstAsid()
148{
149 return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
149 return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
150}
151
152int
153AlphaISA::MiscRegFile::getDataAsid()
154{
150}
151
152int
153AlphaISA::MiscRegFile::getDataAsid()
154{
155 return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
155 return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
156}
157
158#endif
159
160////////////////////////////////////////////////////////////////////////
161//
162//
163//
164void
165AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
166{
167 for (int i = 0; i < NumInternalProcRegs; ++i) {
168 tc->setMiscRegNoEffect(i, 0);
169 }
170
156}
157
158#endif
159
160////////////////////////////////////////////////////////////////////////
161//
162//
163//
164void
165AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
166{
167 for (int i = 0; i < NumInternalProcRegs; ++i) {
168 tc->setMiscRegNoEffect(i, 0);
169 }
170
171 tc->setMiscRegNoEffect(IPR_PAL_BASE, EV5::PalBase);
171 tc->setMiscRegNoEffect(IPR_PAL_BASE, AlphaISA::PalBase);
172 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
173 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
174}
175
176AlphaISA::MiscReg
177AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
178{
179 uint64_t retval = 0; // return value, default 0

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472 tc->getDTBPtr()->flushProcesses();
473 break;
474
475 case AlphaISA::IPR_DTB_IS:
476 // really a control write
477 ipr[idx] = val;
478
479 tc->getDTBPtr()->flushAddr(val,
172 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
173 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
174}
175
176AlphaISA::MiscReg
177AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
178{
179 uint64_t retval = 0; // return value, default 0

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472 tc->getDTBPtr()->flushProcesses();
473 break;
474
475 case AlphaISA::IPR_DTB_IS:
476 // really a control write
477 ipr[idx] = val;
478
479 tc->getDTBPtr()->flushAddr(val,
480 EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
480 AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
481 break;
482
483 case AlphaISA::IPR_DTB_TAG: {
484 struct AlphaISA::TlbEntry entry;
485
486 // FIXME: granularity hints NYI...
481 break;
482
483 case AlphaISA::IPR_DTB_TAG: {
484 struct AlphaISA::TlbEntry entry;
485
486 // FIXME: granularity hints NYI...
487 if (EV5::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
487 if (AlphaISA::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
488 panic("PTE GH field != 0");
489
490 // write entire quad
491 ipr[idx] = val;
492
493 // construct PTE for new entry
488 panic("PTE GH field != 0");
489
490 // write entire quad
491 ipr[idx] = val;
492
493 // construct PTE for new entry
494 entry.ppn = EV5::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
495 entry.xre = EV5::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
496 entry.xwe = EV5::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
497 entry.fonr = EV5::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
498 entry.fonw = EV5::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
499 entry.asma = EV5::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
500 entry.asn = EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
494 entry.ppn = AlphaISA::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
495 entry.xre = AlphaISA::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
496 entry.xwe = AlphaISA::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
497 entry.fonr = AlphaISA::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
498 entry.fonw = AlphaISA::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
499 entry.asma = AlphaISA::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
500 entry.asn = AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
501
502 // insert new TAG/PTE value into data TLB
503 tc->getDTBPtr()->insert(val, entry);
504 }
505 break;
506
507 case AlphaISA::IPR_ITB_PTE: {
508 struct AlphaISA::TlbEntry entry;
509
510 // FIXME: granularity hints NYI...
501
502 // insert new TAG/PTE value into data TLB
503 tc->getDTBPtr()->insert(val, entry);
504 }
505 break;
506
507 case AlphaISA::IPR_ITB_PTE: {
508 struct AlphaISA::TlbEntry entry;
509
510 // FIXME: granularity hints NYI...
511 if (EV5::ITB_PTE_GH(val) != 0)
511 if (AlphaISA::ITB_PTE_GH(val) != 0)
512 panic("PTE GH field != 0");
513
514 // write entire quad
515 ipr[idx] = val;
516
517 // construct PTE for new entry
512 panic("PTE GH field != 0");
513
514 // write entire quad
515 ipr[idx] = val;
516
517 // construct PTE for new entry
518 entry.ppn = EV5::ITB_PTE_PPN(val);
519 entry.xre = EV5::ITB_PTE_XRE(val);
518 entry.ppn = AlphaISA::ITB_PTE_PPN(val);
519 entry.xre = AlphaISA::ITB_PTE_XRE(val);
520 entry.xwe = 0;
520 entry.xwe = 0;
521 entry.fonr = EV5::ITB_PTE_FONR(val);
522 entry.fonw = EV5::ITB_PTE_FONW(val);
523 entry.asma = EV5::ITB_PTE_ASMA(val);
524 entry.asn = EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
521 entry.fonr = AlphaISA::ITB_PTE_FONR(val);
522 entry.fonw = AlphaISA::ITB_PTE_FONW(val);
523 entry.asma = AlphaISA::ITB_PTE_ASMA(val);
524 entry.asn = AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
525
526 // insert new TAG/PTE value into data TLB
527 tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], entry);
528 }
529 break;
530
531 case AlphaISA::IPR_ITB_IA:
532 // really a control write

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542 tc->getITBPtr()->flushProcesses();
543 break;
544
545 case AlphaISA::IPR_ITB_IS:
546 // really a control write
547 ipr[idx] = val;
548
549 tc->getITBPtr()->flushAddr(val,
525
526 // insert new TAG/PTE value into data TLB
527 tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], entry);
528 }
529 break;
530
531 case AlphaISA::IPR_ITB_IA:
532 // really a control write

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542 tc->getITBPtr()->flushProcesses();
543 break;
544
545 case AlphaISA::IPR_ITB_IS:
546 // really a control write
547 ipr[idx] = val;
548
549 tc->getITBPtr()->flushAddr(val,
550 EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
550 AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
551 break;
552
553 default:
554 // invalid IPR
555 panic("Tried to write to invalid ipr %d\n", idx);
556 }
557
558 // no error...

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552
553 default:
554 // invalid IPR
555 panic("Tried to write to invalid ipr %d\n", idx);
556 }
557
558 // no error...

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