ev5.cc (5004:7d94cedab264) ev5.cc (5543:3af77710f397)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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171 tc->setMiscRegNoEffect(IPR_PAL_BASE, EV5::PalBase);
172 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
173 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
174}
175
176AlphaISA::MiscReg
177AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
178{
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 162 unchanged lines hidden (view full) ---

171 tc->setMiscRegNoEffect(IPR_PAL_BASE, EV5::PalBase);
172 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
173 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
174}
175
176AlphaISA::MiscReg
177AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
178{
179 uint64_t retval = 0; // return value, default 0
179 uint64_t retval = 0; // return value, default 0
180
181 switch (idx) {
182 case AlphaISA::IPR_PALtemp0:
183 case AlphaISA::IPR_PALtemp1:
184 case AlphaISA::IPR_PALtemp2:
185 case AlphaISA::IPR_PALtemp3:
186 case AlphaISA::IPR_PALtemp4:
187 case AlphaISA::IPR_PALtemp5:

--- 412 unchanged lines hidden --- 		180
181 switch (idx) {
182 case AlphaISA::IPR_PALtemp0:
183 case AlphaISA::IPR_PALtemp1:
184 case AlphaISA::IPR_PALtemp2:
185 case AlphaISA::IPR_PALtemp3:
186 case AlphaISA::IPR_PALtemp4:
187 case AlphaISA::IPR_PALtemp5:

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