ev5.cc (4395:9acb011a6c35) | ev5.cc (4997:e7380529bd2d) |
---|---|
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 54 unchanged lines hidden (view full) --- 63 AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault; 64 65 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect()); 66 tc->setNextPC(tc->readPC() + sizeof(MachInst)); 67 68 delete reset; 69} 70 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 54 unchanged lines hidden (view full) --- 63 AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault; 64 65 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect()); 66 tc->setNextPC(tc->readPC() + sizeof(MachInst)); 67 68 delete reset; 69} 70 |
71//////////////////////////////////////////////////////////////////////// 72// 73// 74// 75void 76AlphaISA::initIPRs(ThreadContext *tc, int cpuId) 77{ 78 for (int i = 0; i < NumInternalProcRegs; ++i) { 79 tc->setMiscRegNoEffect(i, 0); 80 } | |
81 | 71 |
82 tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase); 83 tc->setMiscRegNoEffect(IPR_MCSR, 0x6); 84 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId); 85} 86 87 | |
88template <class CPU> 89void 90AlphaISA::processInterrupts(CPU *cpu) 91{ 92 //Check if there are any outstanding interrupts 93 //Handle the interrupts 94 int ipl = 0; 95 int summary = 0; --- 70 unchanged lines hidden (view full) --- 166} 167 168int 169AlphaISA::MiscRegFile::getDataAsid() 170{ 171 return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); 172} 173 | 72template <class CPU> 73void 74AlphaISA::processInterrupts(CPU *cpu) 75{ 76 //Check if there are any outstanding interrupts 77 //Handle the interrupts 78 int ipl = 0; 79 int summary = 0; --- 70 unchanged lines hidden (view full) --- 150} 151 152int 153AlphaISA::MiscRegFile::getDataAsid() 154{ 155 return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); 156} 157 |
158#endif 159 160//////////////////////////////////////////////////////////////////////// 161// 162// 163// 164void 165AlphaISA::initIPRs(ThreadContext *tc, int cpuId) 166{ 167 for (int i = 0; i < NumInternalProcRegs; ++i) { 168 tc->setMiscRegNoEffect(i, 0); 169 } 170 171 tc->setMiscRegNoEffect(IPR_PAL_BASE, EV5::PalBase); 172 tc->setMiscRegNoEffect(IPR_MCSR, 0x6); 173 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId); 174} 175 |
|
174AlphaISA::MiscReg 175AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc) 176{ 177 uint64_t retval = 0; // return value, default 0 178 179 switch (idx) { 180 case AlphaISA::IPR_PALtemp0: 181 case AlphaISA::IPR_PALtemp1: --- 153 unchanged lines hidden (view full) --- 335 // isa_desc). 336 ipr[idx] = val; 337 break; 338 339 case AlphaISA::IPR_PALtemp23: 340 // write entire quad w/ no side-effect 341 old = ipr[idx]; 342 ipr[idx] = val; | 176AlphaISA::MiscReg 177AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc) 178{ 179 uint64_t retval = 0; // return value, default 0 180 181 switch (idx) { 182 case AlphaISA::IPR_PALtemp0: 183 case AlphaISA::IPR_PALtemp1: --- 153 unchanged lines hidden (view full) --- 337 // isa_desc). 338 ipr[idx] = val; 339 break; 340 341 case AlphaISA::IPR_PALtemp23: 342 // write entire quad w/ no side-effect 343 old = ipr[idx]; 344 ipr[idx] = val; |
345#if FULL_SYSTEM |
|
343 if (tc->getKernelStats()) 344 tc->getKernelStats()->context(old, val, tc); | 346 if (tc->getKernelStats()) 347 tc->getKernelStats()->context(old, val, tc); |
348#endif |
|
345 break; 346 347 case AlphaISA::IPR_DTB_PTE: 348 // write entire quad w/ no side-effect, tag is forthcoming 349 ipr[idx] = val; 350 break; 351 352 case AlphaISA::IPR_EXC_ADDR: --- 10 unchanged lines hidden (view full) --- 363 case AlphaISA::IPR_IPLR: 364#ifdef DEBUG 365 if (break_ipl != -1 && break_ipl == (val & 0x1f)) 366 debug_break(); 367#endif 368 369 // only write least significant five bits - interrupt level 370 ipr[idx] = val & 0x1f; | 349 break; 350 351 case AlphaISA::IPR_DTB_PTE: 352 // write entire quad w/ no side-effect, tag is forthcoming 353 ipr[idx] = val; 354 break; 355 356 case AlphaISA::IPR_EXC_ADDR: --- 10 unchanged lines hidden (view full) --- 367 case AlphaISA::IPR_IPLR: 368#ifdef DEBUG 369 if (break_ipl != -1 && break_ipl == (val & 0x1f)) 370 debug_break(); 371#endif 372 373 // only write least significant five bits - interrupt level 374 ipr[idx] = val & 0x1f; |
375#if FULL_SYSTEM |
|
371 if (tc->getKernelStats()) 372 tc->getKernelStats()->swpipl(ipr[idx]); | 376 if (tc->getKernelStats()) 377 tc->getKernelStats()->swpipl(ipr[idx]); |
378#endif |
|
373 break; 374 375 case AlphaISA::IPR_DTB_CM: | 379 break; 380 381 case AlphaISA::IPR_DTB_CM: |
382#if FULL_SYSTEM |
|
376 if (val & 0x18) { 377 if (tc->getKernelStats()) 378 tc->getKernelStats()->mode(TheISA::Kernel::user, tc); 379 } else { 380 if (tc->getKernelStats()) 381 tc->getKernelStats()->mode(TheISA::Kernel::kernel, tc); 382 } | 383 if (val & 0x18) { 384 if (tc->getKernelStats()) 385 tc->getKernelStats()->mode(TheISA::Kernel::user, tc); 386 } else { 387 if (tc->getKernelStats()) 388 tc->getKernelStats()->mode(TheISA::Kernel::kernel, tc); 389 } |
390#endif |
|
383 384 case AlphaISA::IPR_ICM: 385 // only write two mode bits - processor mode 386 ipr[idx] = val & 0x18; 387 break; 388 389 case AlphaISA::IPR_ALT_MODE: 390 // only write two mode bits - processor mode --- 72 unchanged lines hidden (view full) --- 463 tc->getDTBPtr()->flushProcesses(); 464 break; 465 466 case AlphaISA::IPR_DTB_IS: 467 // really a control write 468 ipr[idx] = val; 469 470 tc->getDTBPtr()->flushAddr(val, | 391 392 case AlphaISA::IPR_ICM: 393 // only write two mode bits - processor mode 394 ipr[idx] = val & 0x18; 395 break; 396 397 case AlphaISA::IPR_ALT_MODE: 398 // only write two mode bits - processor mode --- 72 unchanged lines hidden (view full) --- 471 tc->getDTBPtr()->flushProcesses(); 472 break; 473 474 case AlphaISA::IPR_DTB_IS: 475 // really a control write 476 ipr[idx] = val; 477 478 tc->getDTBPtr()->flushAddr(val, |
471 DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); | 479 EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); |
472 break; 473 474 case AlphaISA::IPR_DTB_TAG: { 475 struct AlphaISA::PTE pte; 476 477 // FIXME: granularity hints NYI... | 480 break; 481 482 case AlphaISA::IPR_DTB_TAG: { 483 struct AlphaISA::PTE pte; 484 485 // FIXME: granularity hints NYI... |
478 if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) | 486 if (EV5::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) |
479 panic("PTE GH field != 0"); 480 481 // write entire quad 482 ipr[idx] = val; 483 484 // construct PTE for new entry | 487 panic("PTE GH field != 0"); 488 489 // write entire quad 490 ipr[idx] = val; 491 492 // construct PTE for new entry |
485 pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]); 486 pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); 487 pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); 488 pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); 489 pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); 490 pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); 491 pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); | 493 pte.ppn = EV5::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]); 494 pte.xre = EV5::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); 495 pte.xwe = EV5::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); 496 pte.fonr = EV5::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); 497 pte.fonw = EV5::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); 498 pte.asma = EV5::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); 499 pte.asn = EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); |
492 493 // insert new TAG/PTE value into data TLB 494 tc->getDTBPtr()->insert(val, pte); 495 } 496 break; 497 498 case AlphaISA::IPR_ITB_PTE: { 499 struct AlphaISA::PTE pte; 500 501 // FIXME: granularity hints NYI... | 500 501 // insert new TAG/PTE value into data TLB 502 tc->getDTBPtr()->insert(val, pte); 503 } 504 break; 505 506 case AlphaISA::IPR_ITB_PTE: { 507 struct AlphaISA::PTE pte; 508 509 // FIXME: granularity hints NYI... |
502 if (ITB_PTE_GH(val) != 0) | 510 if (EV5::ITB_PTE_GH(val) != 0) |
503 panic("PTE GH field != 0"); 504 505 // write entire quad 506 ipr[idx] = val; 507 508 // construct PTE for new entry | 511 panic("PTE GH field != 0"); 512 513 // write entire quad 514 ipr[idx] = val; 515 516 // construct PTE for new entry |
509 pte.ppn = ITB_PTE_PPN(val); 510 pte.xre = ITB_PTE_XRE(val); | 517 pte.ppn = EV5::ITB_PTE_PPN(val); 518 pte.xre = EV5::ITB_PTE_XRE(val); |
511 pte.xwe = 0; | 519 pte.xwe = 0; |
512 pte.fonr = ITB_PTE_FONR(val); 513 pte.fonw = ITB_PTE_FONW(val); 514 pte.asma = ITB_PTE_ASMA(val); 515 pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); | 520 pte.fonr = EV5::ITB_PTE_FONR(val); 521 pte.fonw = EV5::ITB_PTE_FONW(val); 522 pte.asma = EV5::ITB_PTE_ASMA(val); 523 pte.asn = EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); |
516 517 // insert new TAG/PTE value into data TLB 518 tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); 519 } 520 break; 521 522 case AlphaISA::IPR_ITB_IA: 523 // really a control write --- 9 unchanged lines hidden (view full) --- 533 tc->getITBPtr()->flushProcesses(); 534 break; 535 536 case AlphaISA::IPR_ITB_IS: 537 // really a control write 538 ipr[idx] = val; 539 540 tc->getITBPtr()->flushAddr(val, | 524 525 // insert new TAG/PTE value into data TLB 526 tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); 527 } 528 break; 529 530 case AlphaISA::IPR_ITB_IA: 531 // really a control write --- 9 unchanged lines hidden (view full) --- 541 tc->getITBPtr()->flushProcesses(); 542 break; 543 544 case AlphaISA::IPR_ITB_IS: 545 // really a control write 546 ipr[idx] = val; 547 548 tc->getITBPtr()->flushAddr(val, |
541 ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); | 549 EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); |
542 break; 543 544 default: 545 // invalid IPR 546 panic("Tried to write to invalid ipr %d\n", idx); 547 } 548 549 // no error... 550} 551 552 553void 554AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest) 555{ 556 for (int i = 0; i < NumInternalProcRegs; ++i) { 557 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 558 } 559} 560 | 550 break; 551 552 default: 553 // invalid IPR 554 panic("Tried to write to invalid ipr %d\n", idx); 555 } 556 557 // no error... 558} 559 560 561void 562AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest) 563{ 564 for (int i = 0; i < NumInternalProcRegs; ++i) { 565 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 566 } 567} 568 |
569#if FULL_SYSTEM |
|
561 562/** 563 * Check for special simulator handling of specific PAL calls. 564 * If return value is false, actual PAL call will be suppressed. 565 */ 566bool 567SimpleThread::simPalCheck(int palFunc) 568{ --- 21 unchanged lines hidden --- | 570 571/** 572 * Check for special simulator handling of specific PAL calls. 573 * If return value is false, actual PAL call will be suppressed. 574 */ 575bool 576SimpleThread::simPalCheck(int palFunc) 577{ --- 21 unchanged lines hidden --- |