ev5.cc (4172:141705d83494) ev5.cc (4395:9acb011a6c35)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 231 unchanged lines hidden (view full) ---

240 case AlphaISA::IPR_EXC_SUM:
241 retval = ipr[idx];
242 break;
243
244 case AlphaISA::IPR_DTB_PTE:
245 {
246 AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
247
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 231 unchanged lines hidden (view full) ---

240 case AlphaISA::IPR_EXC_SUM:
241 retval = ipr[idx];
242 break;
243
244 case AlphaISA::IPR_DTB_PTE:
245 {
246 AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
247
248 retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
249 retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
250 retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
251 retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
252 retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
253 retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
254 retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
248 retval |= ((uint64_t)pte.ppn & ULL(0x7ffffff)) << 32;
249 retval |= ((uint64_t)pte.xre & ULL(0xf)) << 8;
250 retval |= ((uint64_t)pte.xwe & ULL(0xf)) << 12;
251 retval |= ((uint64_t)pte.fonr & ULL(0x1)) << 1;
252 retval |= ((uint64_t)pte.fonw & ULL(0x1))<< 2;
253 retval |= ((uint64_t)pte.asma & ULL(0x1)) << 4;
254 retval |= ((uint64_t)pte.asn & ULL(0x7f)) << 57;
255 }
256 break;
257
258 // write only registers
259 case AlphaISA::IPR_HWINT_CLR:
260 case AlphaISA::IPR_SL_XMIT:
261 case AlphaISA::IPR_DC_FLUSH:
262 case AlphaISA::IPR_IC_FLUSH:

--- 327 unchanged lines hidden --- 		255 }
256 break;
257
258 // write only registers
259 case AlphaISA::IPR_HWINT_CLR:
260 case AlphaISA::IPR_SL_XMIT:
261 case AlphaISA::IPR_DC_FLUSH:
262 case AlphaISA::IPR_IC_FLUSH:

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