ev5.cc (3923:a8ce86366fd3) ev5.cc (4172:141705d83494)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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57{
58 initIPRs(tc, cpuId);
59
60 tc->setIntReg(16, cpuId);
61 tc->setIntReg(0, cpuId);
62
63 AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
64
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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57{
58 initIPRs(tc, cpuId);
59
60 tc->setIntReg(16, cpuId);
61 tc->setIntReg(0, cpuId);
62
63 AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
64
65 tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect());
65 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
66 tc->setNextPC(tc->readPC() + sizeof(MachInst));
67
68 delete reset;
69}
70
71////////////////////////////////////////////////////////////////////////
72//
73//
74//
75void
76AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
77{
78 for (int i = 0; i < NumInternalProcRegs; ++i) {
66 tc->setNextPC(tc->readPC() + sizeof(MachInst));
67
68 delete reset;
69}
70
71////////////////////////////////////////////////////////////////////////
72//
73//
74//
75void
76AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
77{
78 for (int i = 0; i < NumInternalProcRegs; ++i) {
79 tc->setMiscReg(i, 0);
79 tc->setMiscRegNoEffect(i, 0);
80 }
81
80 }
81
82 tc->setMiscReg(IPR_PAL_BASE, PalBase);
83 tc->setMiscReg(IPR_MCSR, 0x6);
84 tc->setMiscReg(IPR_PALtemp16, cpuId);
82 tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
83 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
84 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
85}
86
87
88template <class CPU>
89void
90AlphaISA::processInterrupts(CPU *cpu)
91{
92 //Check if there are any outstanding interrupts
93 //Handle the interrupts
94 int ipl = 0;
95 int summary = 0;
96
85}
86
87
88template <class CPU>
89void
90AlphaISA::processInterrupts(CPU *cpu)
91{
92 //Check if there are any outstanding interrupts
93 //Handle the interrupts
94 int ipl = 0;
95 int summary = 0;
96
97 if (cpu->readMiscReg(IPR_ASTRR))
97 if (cpu->readMiscRegNoEffect(IPR_ASTRR))
98 panic("asynchronous traps not implemented\n");
99
98 panic("asynchronous traps not implemented\n");
99
100 if (cpu->readMiscReg(IPR_SIRR)) {
100 if (cpu->readMiscRegNoEffect(IPR_SIRR)) {
101 for (int i = INTLEVEL_SOFTWARE_MIN;
102 i < INTLEVEL_SOFTWARE_MAX; i++) {
101 for (int i = INTLEVEL_SOFTWARE_MIN;
102 i < INTLEVEL_SOFTWARE_MAX; i++) {
103 if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
103 if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
104 // See table 4-19 of the 21164 hardware reference
105 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
106 summary |= (ULL(1) << i);
107 }
108 }
109 }
110
111 uint64_t interrupts = cpu->intr_status();

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116 if (interrupts & (ULL(1) << i)) {
117 // See table 4-19 of the 21164 hardware reference
118 ipl = i;
119 summary |= (ULL(1) << i);
120 }
121 }
122 }
123
104 // See table 4-19 of the 21164 hardware reference
105 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
106 summary |= (ULL(1) << i);
107 }
108 }
109 }
110
111 uint64_t interrupts = cpu->intr_status();

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116 if (interrupts & (ULL(1) << i)) {
117 // See table 4-19 of the 21164 hardware reference
118 ipl = i;
119 summary |= (ULL(1) << i);
120 }
121 }
122 }
123
124 if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
125 cpu->setMiscReg(IPR_ISR, summary);
126 cpu->setMiscReg(IPR_INTID, ipl);
124 if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) {
125 cpu->setMiscRegNoEffect(IPR_ISR, summary);
126 cpu->setMiscRegNoEffect(IPR_INTID, ipl);
127 cpu->trap(new InterruptFault);
128 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
127 cpu->trap(new InterruptFault);
128 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
129 cpu->readMiscReg(IPR_IPLR), ipl, summary);
129 cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
130 }
131
132}
133
134template <class CPU>
135void
136AlphaISA::zeroRegisters(CPU *cpu)
137{

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143}
144
145Fault
146SimpleThread::hwrei()
147{
148 if (!(readPC() & 0x3))
149 return new UnimplementedOpcodeFault;
150
130 }
131
132}
133
134template <class CPU>
135void
136AlphaISA::zeroRegisters(CPU *cpu)
137{

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143}
144
145Fault
146SimpleThread::hwrei()
147{
148 if (!(readPC() & 0x3))
149 return new UnimplementedOpcodeFault;
150
151 setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
151 setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
152
153 if (!misspeculating()) {
154 if (kernelStats)
155 kernelStats->hwrei();
156 }
157
158 // FIXME: XXX check for interrupts? XXX
159 return NoFault;

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549 // no error...
550}
551
552
553void
554AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
555{
556 for (int i = 0; i < NumInternalProcRegs; ++i) {
152
153 if (!misspeculating()) {
154 if (kernelStats)
155 kernelStats->hwrei();
156 }
157
158 // FIXME: XXX check for interrupts? XXX
159 return NoFault;

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549 // no error...
550}
551
552
553void
554AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
555{
556 for (int i = 0; i < NumInternalProcRegs; ++i) {
557 dest->setMiscReg(i, src->readMiscReg(i));
557 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
558 }
559}
560
561
562/**
563 * Check for special simulator handling of specific PAL calls.
564 * If return value is false, actual PAL call will be suppressed.
565 */

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559}
560
561
562/**
563 * Check for special simulator handling of specific PAL calls.
564 * If return value is false, actual PAL call will be suppressed.
565 */

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