ev5.cc (3536:89aa06409e4d) ev5.cc (3548:85e64c82c522)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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35#include "arch/alpha/tlb.hh"
36#include "arch/alpha/kgdb.h"
37#include "base/remote_gdb.hh"
38#include "base/stats/events.hh"
39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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35#include "arch/alpha/tlb.hh"
36#include "arch/alpha/kgdb.h"
37#include "base/remote_gdb.hh"
38#include "base/stats/events.hh"
39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
43#include "kern/kernel_stats.hh"
43#include "kern/alpha/kernel_stats.hh"
44#include "sim/debug.hh"
45#include "sim/sim_exit.hh"
46
47#if FULL_SYSTEM
48
49using namespace EV5;
50
51////////////////////////////////////////////////////////////////////////

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374 ipr[idx] = val & 0x1f;
375 if (tc->getKernelStats())
376 tc->getKernelStats()->swpipl(ipr[idx]);
377 break;
378
379 case AlphaISA::IPR_DTB_CM:
380 if (val & 0x18) {
381 if (tc->getKernelStats())
44#include "sim/debug.hh"
45#include "sim/sim_exit.hh"
46
47#if FULL_SYSTEM
48
49using namespace EV5;
50
51////////////////////////////////////////////////////////////////////////

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374 ipr[idx] = val & 0x1f;
375 if (tc->getKernelStats())
376 tc->getKernelStats()->swpipl(ipr[idx]);
377 break;
378
379 case AlphaISA::IPR_DTB_CM:
380 if (val & 0x18) {
381 if (tc->getKernelStats())
382 tc->getKernelStats()->mode(Kernel::user, tc);
382 tc->getKernelStats()->mode(TheISA::Kernel::user, tc);
383 } else {
384 if (tc->getKernelStats())
383 } else {
384 if (tc->getKernelStats())
385 tc->getKernelStats()->mode(Kernel::kernel, tc);
385 tc->getKernelStats()->mode(TheISA::Kernel::kernel, tc);
386 }
387
388 case AlphaISA::IPR_ICM:
389 // only write two mode bits - processor mode
390 ipr[idx] = val & 0x18;
391 break;
392
393 case AlphaISA::IPR_ALT_MODE:

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387
388 case AlphaISA::IPR_ICM:
389 // only write two mode bits - processor mode
390 ipr[idx] = val & 0x18;
391 break;
392
393 case AlphaISA::IPR_ALT_MODE:

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