ev5.cc (3459:dd091092c8bb) ev5.cc (3468:cf23ad1ceef2)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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55void
56AlphaISA::initCPU(ThreadContext *tc, int cpuId)
57{
58 initIPRs(tc, cpuId);
59
60 tc->setIntReg(16, cpuId);
61 tc->setIntReg(0, cpuId);
62
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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55void
56AlphaISA::initCPU(ThreadContext *tc, int cpuId)
57{
58 initIPRs(tc, cpuId);
59
60 tc->setIntReg(16, cpuId);
61 tc->setIntReg(0, cpuId);
62
63 AlphaFault *reset = new ResetFault;
63 AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
64
65 tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect());
66 tc->setNextPC(tc->readPC() + sizeof(MachInst));
67
68 delete reset;
69}
70
71////////////////////////////////////////////////////////////////////////

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171
172int
173AlphaISA::MiscRegFile::getDataAsid()
174{
175 return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
176}
177
178AlphaISA::MiscReg
64
65 tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect());
66 tc->setNextPC(tc->readPC() + sizeof(MachInst));
67
68 delete reset;
69}
70
71////////////////////////////////////////////////////////////////////////

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171
172int
173AlphaISA::MiscRegFile::getDataAsid()
174{
175 return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
176}
177
178AlphaISA::MiscReg
179AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc)
179AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
180{
181 uint64_t retval = 0; // return value, default 0
182
183 switch (idx) {
184 case AlphaISA::IPR_PALtemp0:
185 case AlphaISA::IPR_PALtemp1:
186 case AlphaISA::IPR_PALtemp2:
187 case AlphaISA::IPR_PALtemp3:

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264 case AlphaISA::IPR_SL_XMIT:
265 case AlphaISA::IPR_DC_FLUSH:
266 case AlphaISA::IPR_IC_FLUSH:
267 case AlphaISA::IPR_ALT_MODE:
268 case AlphaISA::IPR_DTB_IA:
269 case AlphaISA::IPR_DTB_IAP:
270 case AlphaISA::IPR_ITB_IA:
271 case AlphaISA::IPR_ITB_IAP:
180{
181 uint64_t retval = 0; // return value, default 0
182
183 switch (idx) {
184 case AlphaISA::IPR_PALtemp0:
185 case AlphaISA::IPR_PALtemp1:
186 case AlphaISA::IPR_PALtemp2:
187 case AlphaISA::IPR_PALtemp3:

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264 case AlphaISA::IPR_SL_XMIT:
265 case AlphaISA::IPR_DC_FLUSH:
266 case AlphaISA::IPR_IC_FLUSH:
267 case AlphaISA::IPR_ALT_MODE:
268 case AlphaISA::IPR_DTB_IA:
269 case AlphaISA::IPR_DTB_IAP:
270 case AlphaISA::IPR_ITB_IA:
271 case AlphaISA::IPR_ITB_IAP:
272 fault = new UnimplementedOpcodeFault;
272 panic("Tried to read write only register %d\n", idx);
273 break;
274
275 default:
276 // invalid IPR
273 break;
274
275 default:
276 // invalid IPR
277 fault = new UnimplementedOpcodeFault;
277 panic("Tried to read from invalid ipr %d\n", idx);
278 break;
279 }
280
281 return retval;
282}
283
284#ifdef DEBUG
285// Cause the simulator to break when changing to the following IPL
286int break_ipl = -1;
287#endif
288
278 break;
279 }
280
281 return retval;
282}
283
284#ifdef DEBUG
285// Cause the simulator to break when changing to the following IPL
286int break_ipl = -1;
287#endif
288
289Fault
289void
290AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
291{
292 uint64_t old;
293
294 if (tc->misspeculating())
290AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
291{
292 uint64_t old;
293
294 if (tc->misspeculating())
295 return NoFault;
295 return;
296
297 switch (idx) {
298 case AlphaISA::IPR_PALtemp0:
299 case AlphaISA::IPR_PALtemp1:
300 case AlphaISA::IPR_PALtemp2:
301 case AlphaISA::IPR_PALtemp3:
302 case AlphaISA::IPR_PALtemp4:
303 case AlphaISA::IPR_PALtemp5:

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438 break;
439
440 case AlphaISA::IPR_INTID:
441 case AlphaISA::IPR_SL_RCV:
442 case AlphaISA::IPR_MM_STAT:
443 case AlphaISA::IPR_ITB_PTE_TEMP:
444 case AlphaISA::IPR_DTB_PTE_TEMP:
445 // read-only registers
296
297 switch (idx) {
298 case AlphaISA::IPR_PALtemp0:
299 case AlphaISA::IPR_PALtemp1:
300 case AlphaISA::IPR_PALtemp2:
301 case AlphaISA::IPR_PALtemp3:
302 case AlphaISA::IPR_PALtemp4:
303 case AlphaISA::IPR_PALtemp5:

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438 break;
439
440 case AlphaISA::IPR_INTID:
441 case AlphaISA::IPR_SL_RCV:
442 case AlphaISA::IPR_MM_STAT:
443 case AlphaISA::IPR_ITB_PTE_TEMP:
444 case AlphaISA::IPR_DTB_PTE_TEMP:
445 // read-only registers
446 return new UnimplementedOpcodeFault;
446 panic("Tried to write read only ipr %d\n", idx);
447
448 case AlphaISA::IPR_HWINT_CLR:
449 case AlphaISA::IPR_SL_XMIT:
450 case AlphaISA::IPR_DC_FLUSH:
451 case AlphaISA::IPR_IC_FLUSH:
452 // the following are write only
453 ipr[idx] = val;
454 break;

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542 ipr[idx] = val;
543
544 tc->getITBPtr()->flushAddr(val,
545 ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
546 break;
547
548 default:
549 // invalid IPR
447
448 case AlphaISA::IPR_HWINT_CLR:
449 case AlphaISA::IPR_SL_XMIT:
450 case AlphaISA::IPR_DC_FLUSH:
451 case AlphaISA::IPR_IC_FLUSH:
452 // the following are write only
453 ipr[idx] = val;
454 break;

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542 ipr[idx] = val;
543
544 tc->getITBPtr()->flushAddr(val,
545 ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
546 break;
547
548 default:
549 // invalid IPR
550 return new UnimplementedOpcodeFault;
550 panic("Tried to write to invalid ipr %d\n", idx);
551 }
552
553 // no error...
551 }
552
553 // no error...
554 return NoFault;
555}
556
557
558void
559AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
560{
561 for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
562 dest->setMiscReg(i, src->readMiscReg(i));

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555
556
557void
558AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
559{
560 for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
561 dest->setMiscReg(i, src->readMiscReg(i));

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