ev5.cc (2680:246e7104f744) ev5.cc (2683:d6b72bb2ed97)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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32#include "arch/alpha/tlb.hh"
33#include "arch/alpha/isa_traits.hh"
34#include "arch/alpha/osfpal.hh"
35#include "base/kgdb.h"
36#include "base/remote_gdb.hh"
37#include "base/stats/events.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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32#include "arch/alpha/tlb.hh"
33#include "arch/alpha/isa_traits.hh"
34#include "arch/alpha/osfpal.hh"
35#include "base/kgdb.h"
36#include "base/remote_gdb.hh"
37#include "base/stats/events.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/cpu_exec_context.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/thread_context.hh"
42#include "kern/kernel_stats.hh"
43#include "sim/debug.hh"
44#include "sim/sim_events.hh"
45
46#if FULL_SYSTEM
47
48using namespace EV5;

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130
131template <class CPU>
132void
133AlphaISA::zeroRegisters(CPU *cpu)
134{
135 // Insure ISA semantics
136 // (no longer very clean due to the change in setIntReg() in the
137 // cpu model. Consider changing later.)
41#include "cpu/thread_context.hh"
42#include "kern/kernel_stats.hh"
43#include "sim/debug.hh"
44#include "sim/sim_events.hh"
45
46#if FULL_SYSTEM
47
48using namespace EV5;

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130
131template <class CPU>
132void
133AlphaISA::zeroRegisters(CPU *cpu)
134{
135 // Insure ISA semantics
136 // (no longer very clean due to the change in setIntReg() in the
137 // cpu model. Consider changing later.)
138 cpu->cpuXC->setIntReg(ZeroReg, 0);
139 cpu->cpuXC->setFloatReg(ZeroReg, 0.0);
138 cpu->thread->setIntReg(ZeroReg, 0);
139 cpu->thread->setFloatReg(ZeroReg, 0.0);
140}
141
142Fault
140}
141
142Fault
143CPUExecContext::hwrei()
143SimpleThread::hwrei()
144{
145 if (!inPalMode())
146 return new UnimplementedOpcodeFault;
147
148 setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
149
150 if (!misspeculating()) {
151 if (kernelStats)

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557 }
558}
559
560/**
561 * Check for special simulator handling of specific PAL calls.
562 * If return value is false, actual PAL call will be suppressed.
563 */
564bool
144{
145 if (!inPalMode())
146 return new UnimplementedOpcodeFault;
147
148 setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
149
150 if (!misspeculating()) {
151 if (kernelStats)

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557 }
558}
559
560/**
561 * Check for special simulator handling of specific PAL calls.
562 * If return value is false, actual PAL call will be suppressed.
563 */
564bool
565CPUExecContext::simPalCheck(int palFunc)
565SimpleThread::simPalCheck(int palFunc)
566{
567 if (kernelStats)
568 kernelStats->callpal(palFunc, tc);
569
570 switch (palFunc) {
571 case PAL::halt:
572 halt();
573 if (--System::numSystemsRunning == 0)

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567 if (kernelStats)
568 kernelStats->callpal(palFunc, tc);
569
570 switch (palFunc) {
571 case PAL::halt:
572 halt();
573 if (--System::numSystemsRunning == 0)

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