ev5.cc (2670:9107b8bd08cd) | ev5.cc (2680:246e7104f744) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 24 unchanged lines hidden (view full) --- 33#include "arch/alpha/isa_traits.hh" 34#include "arch/alpha/osfpal.hh" 35#include "base/kgdb.h" 36#include "base/remote_gdb.hh" 37#include "base/stats/events.hh" 38#include "config/full_system.hh" 39#include "cpu/base.hh" 40#include "cpu/cpu_exec_context.hh" | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 24 unchanged lines hidden (view full) --- 33#include "arch/alpha/isa_traits.hh" 34#include "arch/alpha/osfpal.hh" 35#include "base/kgdb.h" 36#include "base/remote_gdb.hh" 37#include "base/stats/events.hh" 38#include "config/full_system.hh" 39#include "cpu/base.hh" 40#include "cpu/cpu_exec_context.hh" |
41#include "cpu/exec_context.hh" | 41#include "cpu/thread_context.hh" |
42#include "kern/kernel_stats.hh" 43#include "sim/debug.hh" 44#include "sim/sim_events.hh" 45 46#if FULL_SYSTEM 47 48using namespace EV5; 49 50//////////////////////////////////////////////////////////////////////// 51// 52// Machine dependent functions 53// 54void | 42#include "kern/kernel_stats.hh" 43#include "sim/debug.hh" 44#include "sim/sim_events.hh" 45 46#if FULL_SYSTEM 47 48using namespace EV5; 49 50//////////////////////////////////////////////////////////////////////// 51// 52// Machine dependent functions 53// 54void |
55AlphaISA::initCPU(ExecContext *xc, int cpuId) | 55AlphaISA::initCPU(ThreadContext *tc, int cpuId) |
56{ | 56{ |
57 initIPRs(xc, cpuId); | 57 initIPRs(tc, cpuId); |
58 | 58 |
59 xc->setIntReg(16, cpuId); 60 xc->setIntReg(0, cpuId); | 59 tc->setIntReg(16, cpuId); 60 tc->setIntReg(0, cpuId); |
61 | 61 |
62 xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect()); 63 xc->setNextPC(xc->readPC() + sizeof(MachInst)); | 62 tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect()); 63 tc->setNextPC(tc->readPC() + sizeof(MachInst)); |
64} 65 66//////////////////////////////////////////////////////////////////////// 67// 68// 69// 70void | 64} 65 66//////////////////////////////////////////////////////////////////////// 67// 68// 69// 70void |
71AlphaISA::initIPRs(ExecContext *xc, int cpuId) | 71AlphaISA::initIPRs(ThreadContext *tc, int cpuId) |
72{ 73 for (int i = 0; i < NumInternalProcRegs; ++i) { | 72{ 73 for (int i = 0; i < NumInternalProcRegs; ++i) { |
74 xc->setMiscReg(i, 0); | 74 tc->setMiscReg(i, 0); |
75 } 76 | 75 } 76 |
77 xc->setMiscReg(IPR_PAL_BASE, PalBase); 78 xc->setMiscReg(IPR_MCSR, 0x6); 79 xc->setMiscReg(IPR_PALtemp16, cpuId); | 77 tc->setMiscReg(IPR_PAL_BASE, PalBase); 78 tc->setMiscReg(IPR_MCSR, 0x6); 79 tc->setMiscReg(IPR_PALtemp16, cpuId); |
80} 81 82 83template <class CPU> 84void 85AlphaISA::processInterrupts(CPU *cpu) 86{ 87 //Check if there are any outstanding interrupts --- 78 unchanged lines hidden (view full) --- 166 167int 168AlphaISA::MiscRegFile::getDataAsid() 169{ 170 return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); 171} 172 173AlphaISA::MiscReg | 80} 81 82 83template <class CPU> 84void 85AlphaISA::processInterrupts(CPU *cpu) 86{ 87 //Check if there are any outstanding interrupts --- 78 unchanged lines hidden (view full) --- 166 167int 168AlphaISA::MiscRegFile::getDataAsid() 169{ 170 return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); 171} 172 173AlphaISA::MiscReg |
174AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc) | 174AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc) |
175{ 176 uint64_t retval = 0; // return value, default 0 177 178 switch (idx) { 179 case AlphaISA::IPR_PALtemp0: 180 case AlphaISA::IPR_PALtemp1: 181 case AlphaISA::IPR_PALtemp2: 182 case AlphaISA::IPR_PALtemp3: --- 37 unchanged lines hidden (view full) --- 220 case AlphaISA::IPR_INTID: 221 case AlphaISA::IPR_PMCTR: 222 // no side-effect 223 retval = ipr[idx]; 224 break; 225 226 case AlphaISA::IPR_CC: 227 retval |= ipr[idx] & ULL(0xffffffff00000000); | 175{ 176 uint64_t retval = 0; // return value, default 0 177 178 switch (idx) { 179 case AlphaISA::IPR_PALtemp0: 180 case AlphaISA::IPR_PALtemp1: 181 case AlphaISA::IPR_PALtemp2: 182 case AlphaISA::IPR_PALtemp3: --- 37 unchanged lines hidden (view full) --- 220 case AlphaISA::IPR_INTID: 221 case AlphaISA::IPR_PMCTR: 222 // no side-effect 223 retval = ipr[idx]; 224 break; 225 226 case AlphaISA::IPR_CC: 227 retval |= ipr[idx] & ULL(0xffffffff00000000); |
228 retval |= xc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); | 228 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); |
229 break; 230 231 case AlphaISA::IPR_VA: 232 retval = ipr[idx]; 233 break; 234 235 case AlphaISA::IPR_VA_FORM: 236 case AlphaISA::IPR_MM_STAT: 237 case AlphaISA::IPR_IFAULT_VA_FORM: 238 case AlphaISA::IPR_EXC_MASK: 239 case AlphaISA::IPR_EXC_SUM: 240 retval = ipr[idx]; 241 break; 242 243 case AlphaISA::IPR_DTB_PTE: 244 { | 229 break; 230 231 case AlphaISA::IPR_VA: 232 retval = ipr[idx]; 233 break; 234 235 case AlphaISA::IPR_VA_FORM: 236 case AlphaISA::IPR_MM_STAT: 237 case AlphaISA::IPR_IFAULT_VA_FORM: 238 case AlphaISA::IPR_EXC_MASK: 239 case AlphaISA::IPR_EXC_SUM: 240 retval = ipr[idx]; 241 break; 242 243 case AlphaISA::IPR_DTB_PTE: 244 { |
245 AlphaISA::PTE &pte = xc->getDTBPtr()->index(!xc->misspeculating()); | 245 AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating()); |
246 247 retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; 248 retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; 249 retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; 250 retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; 251 retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; 252 retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; 253 retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; --- 23 unchanged lines hidden (view full) --- 277} 278 279#ifdef DEBUG 280// Cause the simulator to break when changing to the following IPL 281int break_ipl = -1; 282#endif 283 284Fault | 246 247 retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; 248 retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; 249 retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; 250 retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; 251 retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; 252 retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; 253 retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; --- 23 unchanged lines hidden (view full) --- 277} 278 279#ifdef DEBUG 280// Cause the simulator to break when changing to the following IPL 281int break_ipl = -1; 282#endif 283 284Fault |
285AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) | 285AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) |
286{ 287 uint64_t old; 288 | 286{ 287 uint64_t old; 288 |
289 if (xc->misspeculating()) | 289 if (tc->misspeculating()) |
290 return NoFault; 291 292 switch (idx) { 293 case AlphaISA::IPR_PALtemp0: 294 case AlphaISA::IPR_PALtemp1: 295 case AlphaISA::IPR_PALtemp2: 296 case AlphaISA::IPR_PALtemp3: 297 case AlphaISA::IPR_PALtemp4: --- 36 unchanged lines hidden (view full) --- 334 // isa_desc). 335 ipr[idx] = val; 336 break; 337 338 case AlphaISA::IPR_PALtemp23: 339 // write entire quad w/ no side-effect 340 old = ipr[idx]; 341 ipr[idx] = val; | 290 return NoFault; 291 292 switch (idx) { 293 case AlphaISA::IPR_PALtemp0: 294 case AlphaISA::IPR_PALtemp1: 295 case AlphaISA::IPR_PALtemp2: 296 case AlphaISA::IPR_PALtemp3: 297 case AlphaISA::IPR_PALtemp4: --- 36 unchanged lines hidden (view full) --- 334 // isa_desc). 335 ipr[idx] = val; 336 break; 337 338 case AlphaISA::IPR_PALtemp23: 339 // write entire quad w/ no side-effect 340 old = ipr[idx]; 341 ipr[idx] = val; |
342 if (xc->getKernelStats()) 343 xc->getKernelStats()->context(old, val, xc); | 342 if (tc->getKernelStats()) 343 tc->getKernelStats()->context(old, val, tc); |
344 break; 345 346 case AlphaISA::IPR_DTB_PTE: 347 // write entire quad w/ no side-effect, tag is forthcoming 348 ipr[idx] = val; 349 break; 350 351 case AlphaISA::IPR_EXC_ADDR: --- 10 unchanged lines hidden (view full) --- 362 case AlphaISA::IPR_IPLR: 363#ifdef DEBUG 364 if (break_ipl != -1 && break_ipl == (val & 0x1f)) 365 debug_break(); 366#endif 367 368 // only write least significant five bits - interrupt level 369 ipr[idx] = val & 0x1f; | 344 break; 345 346 case AlphaISA::IPR_DTB_PTE: 347 // write entire quad w/ no side-effect, tag is forthcoming 348 ipr[idx] = val; 349 break; 350 351 case AlphaISA::IPR_EXC_ADDR: --- 10 unchanged lines hidden (view full) --- 362 case AlphaISA::IPR_IPLR: 363#ifdef DEBUG 364 if (break_ipl != -1 && break_ipl == (val & 0x1f)) 365 debug_break(); 366#endif 367 368 // only write least significant five bits - interrupt level 369 ipr[idx] = val & 0x1f; |
370 if (xc->getKernelStats()) 371 xc->getKernelStats()->swpipl(ipr[idx]); | 370 if (tc->getKernelStats()) 371 tc->getKernelStats()->swpipl(ipr[idx]); |
372 break; 373 374 case AlphaISA::IPR_DTB_CM: 375 if (val & 0x18) { | 372 break; 373 374 case AlphaISA::IPR_DTB_CM: 375 if (val & 0x18) { |
376 if (xc->getKernelStats()) 377 xc->getKernelStats()->mode(Kernel::user, xc); | 376 if (tc->getKernelStats()) 377 tc->getKernelStats()->mode(Kernel::user, tc); |
378 } else { | 378 } else { |
379 if (xc->getKernelStats()) 380 xc->getKernelStats()->mode(Kernel::kernel, xc); | 379 if (tc->getKernelStats()) 380 tc->getKernelStats()->mode(Kernel::kernel, tc); |
381 } 382 383 case AlphaISA::IPR_ICM: 384 // only write two mode bits - processor mode 385 ipr[idx] = val & 0x18; 386 break; 387 388 case AlphaISA::IPR_ALT_MODE: --- 58 unchanged lines hidden (view full) --- 447 // the following are write only 448 ipr[idx] = val; 449 break; 450 451 case AlphaISA::IPR_DTB_IA: 452 // really a control write 453 ipr[idx] = 0; 454 | 381 } 382 383 case AlphaISA::IPR_ICM: 384 // only write two mode bits - processor mode 385 ipr[idx] = val & 0x18; 386 break; 387 388 case AlphaISA::IPR_ALT_MODE: --- 58 unchanged lines hidden (view full) --- 447 // the following are write only 448 ipr[idx] = val; 449 break; 450 451 case AlphaISA::IPR_DTB_IA: 452 // really a control write 453 ipr[idx] = 0; 454 |
455 xc->getDTBPtr()->flushAll(); | 455 tc->getDTBPtr()->flushAll(); |
456 break; 457 458 case AlphaISA::IPR_DTB_IAP: 459 // really a control write 460 ipr[idx] = 0; 461 | 456 break; 457 458 case AlphaISA::IPR_DTB_IAP: 459 // really a control write 460 ipr[idx] = 0; 461 |
462 xc->getDTBPtr()->flushProcesses(); | 462 tc->getDTBPtr()->flushProcesses(); |
463 break; 464 465 case AlphaISA::IPR_DTB_IS: 466 // really a control write 467 ipr[idx] = val; 468 | 463 break; 464 465 case AlphaISA::IPR_DTB_IS: 466 // really a control write 467 ipr[idx] = val; 468 |
469 xc->getDTBPtr()->flushAddr(val, | 469 tc->getDTBPtr()->flushAddr(val, |
470 DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 471 break; 472 473 case AlphaISA::IPR_DTB_TAG: { 474 struct AlphaISA::PTE pte; 475 476 // FIXME: granularity hints NYI... 477 if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) --- 7 unchanged lines hidden (view full) --- 485 pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); 486 pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); 487 pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); 488 pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); 489 pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); 490 pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); 491 492 // insert new TAG/PTE value into data TLB | 470 DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 471 break; 472 473 case AlphaISA::IPR_DTB_TAG: { 474 struct AlphaISA::PTE pte; 475 476 // FIXME: granularity hints NYI... 477 if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) --- 7 unchanged lines hidden (view full) --- 485 pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); 486 pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); 487 pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); 488 pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); 489 pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); 490 pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); 491 492 // insert new TAG/PTE value into data TLB |
493 xc->getDTBPtr()->insert(val, pte); | 493 tc->getDTBPtr()->insert(val, pte); |
494 } 495 break; 496 497 case AlphaISA::IPR_ITB_PTE: { 498 struct AlphaISA::PTE pte; 499 500 // FIXME: granularity hints NYI... 501 if (ITB_PTE_GH(val) != 0) --- 7 unchanged lines hidden (view full) --- 509 pte.xre = ITB_PTE_XRE(val); 510 pte.xwe = 0; 511 pte.fonr = ITB_PTE_FONR(val); 512 pte.fonw = ITB_PTE_FONW(val); 513 pte.asma = ITB_PTE_ASMA(val); 514 pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); 515 516 // insert new TAG/PTE value into data TLB | 494 } 495 break; 496 497 case AlphaISA::IPR_ITB_PTE: { 498 struct AlphaISA::PTE pte; 499 500 // FIXME: granularity hints NYI... 501 if (ITB_PTE_GH(val) != 0) --- 7 unchanged lines hidden (view full) --- 509 pte.xre = ITB_PTE_XRE(val); 510 pte.xwe = 0; 511 pte.fonr = ITB_PTE_FONR(val); 512 pte.fonw = ITB_PTE_FONW(val); 513 pte.asma = ITB_PTE_ASMA(val); 514 pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); 515 516 // insert new TAG/PTE value into data TLB |
517 xc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); | 517 tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); |
518 } 519 break; 520 521 case AlphaISA::IPR_ITB_IA: 522 // really a control write 523 ipr[idx] = 0; 524 | 518 } 519 break; 520 521 case AlphaISA::IPR_ITB_IA: 522 // really a control write 523 ipr[idx] = 0; 524 |
525 xc->getITBPtr()->flushAll(); | 525 tc->getITBPtr()->flushAll(); |
526 break; 527 528 case AlphaISA::IPR_ITB_IAP: 529 // really a control write 530 ipr[idx] = 0; 531 | 526 break; 527 528 case AlphaISA::IPR_ITB_IAP: 529 // really a control write 530 ipr[idx] = 0; 531 |
532 xc->getITBPtr()->flushProcesses(); | 532 tc->getITBPtr()->flushProcesses(); |
533 break; 534 535 case AlphaISA::IPR_ITB_IS: 536 // really a control write 537 ipr[idx] = val; 538 | 533 break; 534 535 case AlphaISA::IPR_ITB_IS: 536 // really a control write 537 ipr[idx] = val; 538 |
539 xc->getITBPtr()->flushAddr(val, | 539 tc->getITBPtr()->flushAddr(val, |
540 ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); 541 break; 542 543 default: 544 // invalid IPR 545 return new UnimplementedOpcodeFault; 546 } 547 548 // no error... 549 return NoFault; 550} 551 552void | 540 ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); 541 break; 542 543 default: 544 // invalid IPR 545 return new UnimplementedOpcodeFault; 546 } 547 548 // no error... 549 return NoFault; 550} 551 552void |
553AlphaISA::copyIprs(ExecContext *src, ExecContext *dest) | 553AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest) |
554{ 555 for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) { 556 dest->setMiscReg(i, src->readMiscReg(i)); 557 } 558} 559 560/** 561 * Check for special simulator handling of specific PAL calls. 562 * If return value is false, actual PAL call will be suppressed. 563 */ 564bool 565CPUExecContext::simPalCheck(int palFunc) 566{ 567 if (kernelStats) | 554{ 555 for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) { 556 dest->setMiscReg(i, src->readMiscReg(i)); 557 } 558} 559 560/** 561 * Check for special simulator handling of specific PAL calls. 562 * If return value is false, actual PAL call will be suppressed. 563 */ 564bool 565CPUExecContext::simPalCheck(int palFunc) 566{ 567 if (kernelStats) |
568 kernelStats->callpal(palFunc, proxy); | 568 kernelStats->callpal(palFunc, tc); |
569 570 switch (palFunc) { 571 case PAL::halt: 572 halt(); 573 if (--System::numSystemsRunning == 0) 574 new SimExitEvent("all cpus halted"); 575 break; 576 577 case PAL::bpt: 578 case PAL::bugchk: 579 if (system->breakpoint()) 580 return false; 581 break; 582 } 583 584 return true; 585} 586 587#endif // FULL_SYSTEM | 569 570 switch (palFunc) { 571 case PAL::halt: 572 halt(); 573 if (--System::numSystemsRunning == 0) 574 new SimExitEvent("all cpus halted"); 575 break; 576 577 case PAL::bpt: 578 case PAL::bugchk: 579 if (system->breakpoint()) 580 return false; 581 break; 582 } 583 584 return true; 585} 586 587#endif // FULL_SYSTEM |