ev5.cc (11299:72046b9b3323) | ev5.cc (12406:86bde4a026b5) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38#include "base/debug.hh" 39#include "cpu/base.hh" 40#include "cpu/simple_thread.hh" 41#include "cpu/thread_context.hh" 42#include "sim/sim_exit.hh" 43 44namespace AlphaISA { 45 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38#include "base/debug.hh" 39#include "cpu/base.hh" 40#include "cpu/simple_thread.hh" 41#include "cpu/thread_context.hh" 42#include "sim/sim_exit.hh" 43 44namespace AlphaISA { 45 |
46template<typename T> 47TLB * 48getITBPtr(T *tc) 49{ 50 auto tlb = dynamic_cast<TLB *>(tc->getITBPtr()); 51 assert(tlb); 52 return tlb; 53} 54 55template<typename T> 56TLB * 57getDTBPtr(T *tc) 58{ 59 auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr()); 60 assert(tlb); 61 return tlb; 62} 63 |
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46//////////////////////////////////////////////////////////////////////// 47// 48// Machine dependent functions 49// 50void 51initCPU(ThreadContext *tc, int cpuId) 52{ 53 initIPRs(tc, cpuId); --- 102 unchanged lines hidden (view full) --- 156 case IPR_IFAULT_VA_FORM: 157 case IPR_EXC_MASK: 158 case IPR_EXC_SUM: 159 retval = ipr[idx]; 160 break; 161 162 case IPR_DTB_PTE: 163 { | 64//////////////////////////////////////////////////////////////////////// 65// 66// Machine dependent functions 67// 68void 69initCPU(ThreadContext *tc, int cpuId) 70{ 71 initIPRs(tc, cpuId); --- 102 unchanged lines hidden (view full) --- 174 case IPR_IFAULT_VA_FORM: 175 case IPR_EXC_MASK: 176 case IPR_EXC_SUM: 177 retval = ipr[idx]; 178 break; 179 180 case IPR_DTB_PTE: 181 { |
164 TlbEntry &entry = tc->getDTBPtr()->index(1); | 182 TlbEntry &entry = getDTBPtr(tc)->index(1); |
165 166 retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32; 167 retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8; 168 retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12; 169 retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1; 170 retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2; 171 retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4; 172 retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57; --- 180 unchanged lines hidden (view full) --- 353 // the following are write only 354 ipr[idx] = val; 355 break; 356 357 case IPR_DTB_IA: 358 // really a control write 359 ipr[idx] = 0; 360 | 183 184 retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32; 185 retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8; 186 retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12; 187 retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1; 188 retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2; 189 retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4; 190 retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57; --- 180 unchanged lines hidden (view full) --- 371 // the following are write only 372 ipr[idx] = val; 373 break; 374 375 case IPR_DTB_IA: 376 // really a control write 377 ipr[idx] = 0; 378 |
361 tc->getDTBPtr()->flushAll(); | 379 getDTBPtr(tc)->flushAll(); |
362 break; 363 364 case IPR_DTB_IAP: 365 // really a control write 366 ipr[idx] = 0; 367 | 380 break; 381 382 case IPR_DTB_IAP: 383 // really a control write 384 ipr[idx] = 0; 385 |
368 tc->getDTBPtr()->flushProcesses(); | 386 getDTBPtr(tc)->flushProcesses(); |
369 break; 370 371 case IPR_DTB_IS: 372 // really a control write 373 ipr[idx] = val; 374 | 387 break; 388 389 case IPR_DTB_IS: 390 // really a control write 391 ipr[idx] = val; 392 |
375 tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN])); | 393 getDTBPtr(tc)->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN])); |
376 break; 377 378 case IPR_DTB_TAG: { 379 struct TlbEntry entry; 380 381 // FIXME: granularity hints NYI... 382 if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0) 383 panic("PTE GH field != 0"); --- 6 unchanged lines hidden (view full) --- 390 entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]); 391 entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]); 392 entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]); 393 entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]); 394 entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]); 395 entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]); 396 397 // insert new TAG/PTE value into data TLB | 394 break; 395 396 case IPR_DTB_TAG: { 397 struct TlbEntry entry; 398 399 // FIXME: granularity hints NYI... 400 if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0) 401 panic("PTE GH field != 0"); --- 6 unchanged lines hidden (view full) --- 408 entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]); 409 entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]); 410 entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]); 411 entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]); 412 entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]); 413 entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]); 414 415 // insert new TAG/PTE value into data TLB |
398 tc->getDTBPtr()->insert(val, entry); | 416 getDTBPtr(tc)->insert(val, entry); |
399 } 400 break; 401 402 case IPR_ITB_PTE: { 403 struct TlbEntry entry; 404 405 // FIXME: granularity hints NYI... 406 if (ITB_PTE_GH(val) != 0) --- 7 unchanged lines hidden (view full) --- 414 entry.xre = ITB_PTE_XRE(val); 415 entry.xwe = 0; 416 entry.fonr = ITB_PTE_FONR(val); 417 entry.fonw = ITB_PTE_FONW(val); 418 entry.asma = ITB_PTE_ASMA(val); 419 entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]); 420 421 // insert new TAG/PTE value into data TLB | 417 } 418 break; 419 420 case IPR_ITB_PTE: { 421 struct TlbEntry entry; 422 423 // FIXME: granularity hints NYI... 424 if (ITB_PTE_GH(val) != 0) --- 7 unchanged lines hidden (view full) --- 432 entry.xre = ITB_PTE_XRE(val); 433 entry.xwe = 0; 434 entry.fonr = ITB_PTE_FONR(val); 435 entry.fonw = ITB_PTE_FONW(val); 436 entry.asma = ITB_PTE_ASMA(val); 437 entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]); 438 439 // insert new TAG/PTE value into data TLB |
422 tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry); | 440 getITBPtr(tc)->insert(ipr[IPR_ITB_TAG], entry); |
423 } 424 break; 425 426 case IPR_ITB_IA: 427 // really a control write 428 ipr[idx] = 0; 429 | 441 } 442 break; 443 444 case IPR_ITB_IA: 445 // really a control write 446 ipr[idx] = 0; 447 |
430 tc->getITBPtr()->flushAll(); | 448 getITBPtr(tc)->flushAll(); |
431 break; 432 433 case IPR_ITB_IAP: 434 // really a control write 435 ipr[idx] = 0; 436 | 449 break; 450 451 case IPR_ITB_IAP: 452 // really a control write 453 ipr[idx] = 0; 454 |
437 tc->getITBPtr()->flushProcesses(); | 455 getITBPtr(tc)->flushProcesses(); |
438 break; 439 440 case IPR_ITB_IS: 441 // really a control write 442 ipr[idx] = val; 443 | 456 break; 457 458 case IPR_ITB_IS: 459 // really a control write 460 ipr[idx] = val; 461 |
444 tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN])); | 462 getITBPtr(tc)->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN])); |
445 break; 446 447 default: 448 // invalid IPR 449 panic("Tried to write to invalid ipr %d\n", idx); 450 } 451 452 // no error... --- 58 unchanged lines hidden --- | 463 break; 464 465 default: 466 // invalid IPR 467 panic("Tried to write to invalid ipr %d\n", idx); 468 } 469 470 // no error... --- 58 unchanged lines hidden --- |