ev5.cc (10664:61a0b02aa800) ev5.cc (11299:72046b9b3323)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 257 unchanged lines hidden (view full) ---

266
267 case IPR_ASTRR:
268 case IPR_ASTER:
269 // only write least significant four bits - privilege mask
270 ipr[idx] = val & 0xf;
271 break;
272
273 case IPR_IPLR:
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 257 unchanged lines hidden (view full) ---

266
267 case IPR_ASTRR:
268 case IPR_ASTER:
269 // only write least significant four bits - privilege mask
270 ipr[idx] = val & 0xf;
271 break;
272
273 case IPR_IPLR:
274#ifdef DEBUG
275 if (break_ipl != -1 && break_ipl == (int)(val & 0x1f))
276 Debug::breakpoint();
277#endif
278
279 // only write least significant five bits - interrupt level
280 ipr[idx] = val & 0x1f;
281 if (tc->getKernelStats())
282 tc->getKernelStats()->swpipl(ipr[idx]);
283 break;
284
285 case IPR_DTB_CM:
286 if (val & 0x18) {

--- 229 unchanged lines hidden --- 		274 // only write least significant five bits - interrupt level
275 ipr[idx] = val & 0x1f;
276 if (tc->getKernelStats())
277 tc->getKernelStats()->swpipl(ipr[idx]);
278 break;
279
280 case IPR_DTB_CM:
281 if (val & 0x18) {

--- 229 unchanged lines hidden ---