ev5.cc (10474:799c8ee4ecba) ev5.cc (10664:61a0b02aa800)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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156 case IPR_IFAULT_VA_FORM:
157 case IPR_EXC_MASK:
158 case IPR_EXC_SUM:
159 retval = ipr[idx];
160 break;
161
162 case IPR_DTB_PTE:
163 {
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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156 case IPR_IFAULT_VA_FORM:
157 case IPR_EXC_MASK:
158 case IPR_EXC_SUM:
159 retval = ipr[idx];
160 break;
161
162 case IPR_DTB_PTE:
163 {
164 TlbEntry &entry
165 = tc->getDTBPtr()->index(!tc->misspeculating());
164 TlbEntry &entry = tc->getDTBPtr()->index(1);
166
167 retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
168 retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
169 retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12;
170 retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1;
171 retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2;
172 retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4;
173 retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57;

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197}
198
199// Cause the simulator to break when changing to the following IPL
200int break_ipl = -1;
201
202void
203ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
204{
165
166 retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
167 retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
168 retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12;
169 retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1;
170 retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2;
171 retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4;
172 retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57;

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196}
197
198// Cause the simulator to break when changing to the following IPL
199int break_ipl = -1;
200
201void
202ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
203{
205 if (tc->misspeculating())
206 return;
207
208 switch (idx) {
209 case IPR_PALtemp0:
210 case IPR_PALtemp1:
211 case IPR_PALtemp2:
212 case IPR_PALtemp3:
213 case IPR_PALtemp4:
214 case IPR_PALtemp5:
215 case IPR_PALtemp6:

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479 if (!(pc.pc() & 0x3))
480 return std::make_shared<UnimplementedOpcodeFault>();
481
482 pc.npc(readMiscRegNoEffect(IPR_EXC_ADDR));
483 pcState(pc);
484
485 CPA::cpa()->swAutoBegin(tc, pc.npc());
486
204 switch (idx) {
205 case IPR_PALtemp0:
206 case IPR_PALtemp1:
207 case IPR_PALtemp2:
208 case IPR_PALtemp3:
209 case IPR_PALtemp4:
210 case IPR_PALtemp5:
211 case IPR_PALtemp6:

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475 if (!(pc.pc() & 0x3))
476 return std::make_shared<UnimplementedOpcodeFault>();
477
478 pc.npc(readMiscRegNoEffect(IPR_EXC_ADDR));
479 pcState(pc);
480
481 CPA::cpa()->swAutoBegin(tc, pc.npc());
482
487 if (!misspeculating()) {
488 if (kernelStats)
489 kernelStats->hwrei();
490 }
483 if (kernelStats)
484 kernelStats->hwrei();
491
492 // FIXME: XXX check for interrupts? XXX
493 return NoFault;
494}
495
496/**
497 * Check for special simulator handling of specific PAL calls.
498 * If return value is false, actual PAL call will be suppressed.

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486 // FIXME: XXX check for interrupts? XXX
487 return NoFault;
488}
489
490/**
491 * Check for special simulator handling of specific PAL calls.
492 * If return value is false, actual PAL call will be suppressed.

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