1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#include "arch/alpha/faults.hh" 33#include "arch/alpha/isa_traits.hh" 34#include "arch/alpha/kernel_stats.hh" 35#include "arch/alpha/osfpal.hh" 36#include "arch/alpha/tlb.hh" 37#include "arch/alpha/kgdb.h" 38#include "base/remote_gdb.hh" 39#include "base/stats/events.hh" 40#include "config/full_system.hh" 41#include "cpu/base.hh" 42#include "cpu/simple_thread.hh" 43#include "cpu/thread_context.hh" 44#include "sim/debug.hh" 45#include "sim/sim_exit.hh" 46
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47using namespace AlphaISA;
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47namespace AlphaISA { |
48 49#if FULL_SYSTEM 50 51//////////////////////////////////////////////////////////////////////// 52// 53// Machine dependent functions 54// 55void
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56AlphaISA::initCPU(ThreadContext *tc, int cpuId)
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56initCPU(ThreadContext *tc, int cpuId) |
57{ 58 initIPRs(tc, cpuId); 59 60 tc->setIntReg(16, cpuId); 61 tc->setIntReg(0, cpuId); 62
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63 AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
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63 AlphaFault *reset = new ResetFault; |
64 65 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect()); 66 tc->setNextPC(tc->readPC() + sizeof(MachInst)); 67 68 delete reset; 69} 70 71 72template <class CPU> 73void
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74AlphaISA::processInterrupts(CPU *cpu)
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74processInterrupts(CPU *cpu) |
75{ 76 //Check if there are any outstanding interrupts 77 //Handle the interrupts 78 int ipl = 0; 79 int summary = 0; 80 81 if (cpu->readMiscRegNoEffect(IPR_ASTRR)) 82 panic("asynchronous traps not implemented\n"); 83 84 if (cpu->readMiscRegNoEffect(IPR_SIRR)) { 85 for (int i = INTLEVEL_SOFTWARE_MIN; 86 i < INTLEVEL_SOFTWARE_MAX; i++) { 87 if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { 88 // See table 4-19 of the 21164 hardware reference 89 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 90 summary |= (ULL(1) << i); 91 } 92 } 93 } 94 95 uint64_t interrupts = cpu->intr_status(); 96 97 if (interrupts) { 98 for (int i = INTLEVEL_EXTERNAL_MIN; 99 i < INTLEVEL_EXTERNAL_MAX; i++) { 100 if (interrupts & (ULL(1) << i)) { 101 // See table 4-19 of the 21164 hardware reference 102 ipl = i; 103 summary |= (ULL(1) << i); 104 } 105 } 106 } 107 108 if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) { 109 cpu->setMiscRegNoEffect(IPR_ISR, summary); 110 cpu->setMiscRegNoEffect(IPR_INTID, ipl); 111 cpu->trap(new InterruptFault); 112 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 113 cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary); 114 } 115 116} 117 118template <class CPU> 119void
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120AlphaISA::zeroRegisters(CPU *cpu)
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120zeroRegisters(CPU *cpu) |
121{ 122 // Insure ISA semantics 123 // (no longer very clean due to the change in setIntReg() in the 124 // cpu model. Consider changing later.) 125 cpu->thread->setIntReg(ZeroReg, 0); 126 cpu->thread->setFloatReg(ZeroReg, 0.0); 127} 128
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129Fault
130SimpleThread::hwrei()
131{
132 if (!(readPC() & 0x3))
133 return new UnimplementedOpcodeFault;
134
135 setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
136
137 if (!misspeculating()) {
138 if (kernelStats)
139 kernelStats->hwrei();
140 }
141
142 // FIXME: XXX check for interrupts? XXX
143 return NoFault;
144}
145
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129int
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147AlphaISA::MiscRegFile::getInstAsid()
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130MiscRegFile::getInstAsid() |
131{
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149 return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
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132 return ITB_ASN_ASN(ipr[IPR_ITB_ASN]); |
133} 134 135int
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153AlphaISA::MiscRegFile::getDataAsid()
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136MiscRegFile::getDataAsid() |
137{
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155 return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
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138 return DTB_ASN_ASN(ipr[IPR_DTB_ASN]); |
139} 140 141#endif 142 143//////////////////////////////////////////////////////////////////////// 144// 145// 146// 147void
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165AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
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148initIPRs(ThreadContext *tc, int cpuId) |
149{ 150 for (int i = 0; i < NumInternalProcRegs; ++i) { 151 tc->setMiscRegNoEffect(i, 0); 152 } 153
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171 tc->setMiscRegNoEffect(IPR_PAL_BASE, AlphaISA::PalBase);
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154 tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase); |
155 tc->setMiscRegNoEffect(IPR_MCSR, 0x6); 156 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId); 157} 158
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176AlphaISA::MiscReg
177AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
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159MiscReg 160MiscRegFile::readIpr(int idx, ThreadContext *tc) |
161{ 162 uint64_t retval = 0; // return value, default 0 163 164 switch (idx) {
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182 case AlphaISA::IPR_PALtemp0:
183 case AlphaISA::IPR_PALtemp1:
184 case AlphaISA::IPR_PALtemp2:
185 case AlphaISA::IPR_PALtemp3:
186 case AlphaISA::IPR_PALtemp4:
187 case AlphaISA::IPR_PALtemp5:
188 case AlphaISA::IPR_PALtemp6:
189 case AlphaISA::IPR_PALtemp7:
190 case AlphaISA::IPR_PALtemp8:
191 case AlphaISA::IPR_PALtemp9:
192 case AlphaISA::IPR_PALtemp10:
193 case AlphaISA::IPR_PALtemp11:
194 case AlphaISA::IPR_PALtemp12:
195 case AlphaISA::IPR_PALtemp13:
196 case AlphaISA::IPR_PALtemp14:
197 case AlphaISA::IPR_PALtemp15:
198 case AlphaISA::IPR_PALtemp16:
199 case AlphaISA::IPR_PALtemp17:
200 case AlphaISA::IPR_PALtemp18:
201 case AlphaISA::IPR_PALtemp19:
202 case AlphaISA::IPR_PALtemp20:
203 case AlphaISA::IPR_PALtemp21:
204 case AlphaISA::IPR_PALtemp22:
205 case AlphaISA::IPR_PALtemp23:
206 case AlphaISA::IPR_PAL_BASE:
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165 case IPR_PALtemp0: 166 case IPR_PALtemp1: 167 case IPR_PALtemp2: 168 case IPR_PALtemp3: 169 case IPR_PALtemp4: 170 case IPR_PALtemp5: 171 case IPR_PALtemp6: 172 case IPR_PALtemp7: 173 case IPR_PALtemp8: 174 case IPR_PALtemp9: 175 case IPR_PALtemp10: 176 case IPR_PALtemp11: 177 case IPR_PALtemp12: 178 case IPR_PALtemp13: 179 case IPR_PALtemp14: 180 case IPR_PALtemp15: 181 case IPR_PALtemp16: 182 case IPR_PALtemp17: 183 case IPR_PALtemp18: 184 case IPR_PALtemp19: 185 case IPR_PALtemp20: 186 case IPR_PALtemp21: 187 case IPR_PALtemp22: 188 case IPR_PALtemp23: 189 case IPR_PAL_BASE: |
190
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208 case AlphaISA::IPR_IVPTBR:
209 case AlphaISA::IPR_DC_MODE:
210 case AlphaISA::IPR_MAF_MODE:
211 case AlphaISA::IPR_ISR:
212 case AlphaISA::IPR_EXC_ADDR:
213 case AlphaISA::IPR_IC_PERR_STAT:
214 case AlphaISA::IPR_DC_PERR_STAT:
215 case AlphaISA::IPR_MCSR:
216 case AlphaISA::IPR_ASTRR:
217 case AlphaISA::IPR_ASTER:
218 case AlphaISA::IPR_SIRR:
219 case AlphaISA::IPR_ICSR:
220 case AlphaISA::IPR_ICM:
221 case AlphaISA::IPR_DTB_CM:
222 case AlphaISA::IPR_IPLR:
223 case AlphaISA::IPR_INTID:
224 case AlphaISA::IPR_PMCTR:
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191 case IPR_IVPTBR: 192 case IPR_DC_MODE: 193 case IPR_MAF_MODE: 194 case IPR_ISR: 195 case IPR_EXC_ADDR: 196 case IPR_IC_PERR_STAT: 197 case IPR_DC_PERR_STAT: 198 case IPR_MCSR: 199 case IPR_ASTRR: 200 case IPR_ASTER: 201 case IPR_SIRR: 202 case IPR_ICSR: 203 case IPR_ICM: 204 case IPR_DTB_CM: 205 case IPR_IPLR: 206 case IPR_INTID: 207 case IPR_PMCTR: |
208 // no side-effect 209 retval = ipr[idx]; 210 break; 211
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229 case AlphaISA::IPR_CC:
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212 case IPR_CC: |
213 retval |= ipr[idx] & ULL(0xffffffff00000000); 214 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); 215 break; 216
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234 case AlphaISA::IPR_VA:
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217 case IPR_VA: |
218 retval = ipr[idx]; 219 break; 220
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238 case AlphaISA::IPR_VA_FORM:
239 case AlphaISA::IPR_MM_STAT:
240 case AlphaISA::IPR_IFAULT_VA_FORM:
241 case AlphaISA::IPR_EXC_MASK:
242 case AlphaISA::IPR_EXC_SUM:
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221 case IPR_VA_FORM: 222 case IPR_MM_STAT: 223 case IPR_IFAULT_VA_FORM: 224 case IPR_EXC_MASK: 225 case IPR_EXC_SUM: |
226 retval = ipr[idx]; 227 break; 228
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246 case AlphaISA::IPR_DTB_PTE:
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229 case IPR_DTB_PTE: |
230 {
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248 AlphaISA::TlbEntry &entry
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231 TlbEntry &entry |
232 = tc->getDTBPtr()->index(!tc->misspeculating()); 233 234 retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32; 235 retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8; 236 retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12; 237 retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1; 238 retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2; 239 retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4; 240 retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57; 241 } 242 break; 243 244 // write only registers
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262 case AlphaISA::IPR_HWINT_CLR:
263 case AlphaISA::IPR_SL_XMIT:
264 case AlphaISA::IPR_DC_FLUSH:
265 case AlphaISA::IPR_IC_FLUSH:
266 case AlphaISA::IPR_ALT_MODE:
267 case AlphaISA::IPR_DTB_IA:
268 case AlphaISA::IPR_DTB_IAP:
269 case AlphaISA::IPR_ITB_IA:
270 case AlphaISA::IPR_ITB_IAP:
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245 case IPR_HWINT_CLR: 246 case IPR_SL_XMIT: 247 case IPR_DC_FLUSH: 248 case IPR_IC_FLUSH: 249 case IPR_ALT_MODE: 250 case IPR_DTB_IA: 251 case IPR_DTB_IAP: 252 case IPR_ITB_IA: 253 case IPR_ITB_IAP: |
254 panic("Tried to read write only register %d\n", idx); 255 break; 256 257 default: 258 // invalid IPR 259 panic("Tried to read from invalid ipr %d\n", idx); 260 break; 261 } 262 263 return retval; 264} 265 266#ifdef DEBUG 267// Cause the simulator to break when changing to the following IPL 268int break_ipl = -1; 269#endif 270 271void
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289AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
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272MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) |
273{ 274 uint64_t old; 275 276 if (tc->misspeculating()) 277 return; 278 279 switch (idx) {
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297 case AlphaISA::IPR_PALtemp0:
298 case AlphaISA::IPR_PALtemp1:
299 case AlphaISA::IPR_PALtemp2:
300 case AlphaISA::IPR_PALtemp3:
301 case AlphaISA::IPR_PALtemp4:
302 case AlphaISA::IPR_PALtemp5:
303 case AlphaISA::IPR_PALtemp6:
304 case AlphaISA::IPR_PALtemp7:
305 case AlphaISA::IPR_PALtemp8:
306 case AlphaISA::IPR_PALtemp9:
307 case AlphaISA::IPR_PALtemp10:
308 case AlphaISA::IPR_PALtemp11:
309 case AlphaISA::IPR_PALtemp12:
310 case AlphaISA::IPR_PALtemp13:
311 case AlphaISA::IPR_PALtemp14:
312 case AlphaISA::IPR_PALtemp15:
313 case AlphaISA::IPR_PALtemp16:
314 case AlphaISA::IPR_PALtemp17:
315 case AlphaISA::IPR_PALtemp18:
316 case AlphaISA::IPR_PALtemp19:
317 case AlphaISA::IPR_PALtemp20:
318 case AlphaISA::IPR_PALtemp21:
319 case AlphaISA::IPR_PALtemp22:
320 case AlphaISA::IPR_PAL_BASE:
321 case AlphaISA::IPR_IC_PERR_STAT:
322 case AlphaISA::IPR_DC_PERR_STAT:
323 case AlphaISA::IPR_PMCTR:
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280 case IPR_PALtemp0: 281 case IPR_PALtemp1: 282 case IPR_PALtemp2: 283 case IPR_PALtemp3: 284 case IPR_PALtemp4: 285 case IPR_PALtemp5: 286 case IPR_PALtemp6: 287 case IPR_PALtemp7: 288 case IPR_PALtemp8: 289 case IPR_PALtemp9: 290 case IPR_PALtemp10: 291 case IPR_PALtemp11: 292 case IPR_PALtemp12: 293 case IPR_PALtemp13: 294 case IPR_PALtemp14: 295 case IPR_PALtemp15: 296 case IPR_PALtemp16: 297 case IPR_PALtemp17: 298 case IPR_PALtemp18: 299 case IPR_PALtemp19: 300 case IPR_PALtemp20: 301 case IPR_PALtemp21: 302 case IPR_PALtemp22: 303 case IPR_PAL_BASE: 304 case IPR_IC_PERR_STAT: 305 case IPR_DC_PERR_STAT: 306 case IPR_PMCTR: |
307 // write entire quad w/ no side-effect 308 ipr[idx] = val; 309 break; 310
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328 case AlphaISA::IPR_CC_CTL:
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311 case IPR_CC_CTL: |
312 // This IPR resets the cycle counter. We assume this only 313 // happens once... let's verify that. 314 assert(ipr[idx] == 0); 315 ipr[idx] = 1; 316 break; 317
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335 case AlphaISA::IPR_CC:
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318 case IPR_CC: |
319 // This IPR only writes the upper 64 bits. It's ok to write 320 // all 64 here since we mask out the lower 32 in rpcc (see 321 // isa_desc). 322 ipr[idx] = val; 323 break; 324
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342 case AlphaISA::IPR_PALtemp23:
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325 case IPR_PALtemp23: |
326 // write entire quad w/ no side-effect 327 old = ipr[idx]; 328 ipr[idx] = val; 329#if FULL_SYSTEM 330 if (tc->getKernelStats()) 331 tc->getKernelStats()->context(old, val, tc); 332#endif 333 break; 334
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352 case AlphaISA::IPR_DTB_PTE:
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335 case IPR_DTB_PTE: |
336 // write entire quad w/ no side-effect, tag is forthcoming 337 ipr[idx] = val; 338 break; 339
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357 case AlphaISA::IPR_EXC_ADDR:
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340 case IPR_EXC_ADDR: |
341 // second least significant bit in PC is always zero 342 ipr[idx] = val & ~2; 343 break; 344
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362 case AlphaISA::IPR_ASTRR:
363 case AlphaISA::IPR_ASTER:
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345 case IPR_ASTRR: 346 case IPR_ASTER: |
347 // only write least significant four bits - privilege mask 348 ipr[idx] = val & 0xf; 349 break; 350
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368 case AlphaISA::IPR_IPLR:
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351 case IPR_IPLR: |
352#ifdef DEBUG 353 if (break_ipl != -1 && break_ipl == (val & 0x1f)) 354 debug_break(); 355#endif 356 357 // only write least significant five bits - interrupt level 358 ipr[idx] = val & 0x1f; 359#if FULL_SYSTEM 360 if (tc->getKernelStats()) 361 tc->getKernelStats()->swpipl(ipr[idx]); 362#endif 363 break; 364
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382 case AlphaISA::IPR_DTB_CM:
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365 case IPR_DTB_CM: |
366#if FULL_SYSTEM 367 if (val & 0x18) { 368 if (tc->getKernelStats())
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386 tc->getKernelStats()->mode(AlphaISA::Kernel::user, tc);
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369 tc->getKernelStats()->mode(Kernel::user, tc); |
370 } else { 371 if (tc->getKernelStats())
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389 tc->getKernelStats()->mode(AlphaISA::Kernel::kernel, tc);
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372 tc->getKernelStats()->mode(Kernel::kernel, tc); |
373 } 374#endif 375
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393 case AlphaISA::IPR_ICM:
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376 case IPR_ICM: |
377 // only write two mode bits - processor mode 378 ipr[idx] = val & 0x18; 379 break; 380
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398 case AlphaISA::IPR_ALT_MODE:
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381 case IPR_ALT_MODE: |
382 // only write two mode bits - processor mode 383 ipr[idx] = val & 0x18; 384 break; 385
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403 case AlphaISA::IPR_MCSR:
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386 case IPR_MCSR: |
387 // more here after optimization... 388 ipr[idx] = val; 389 break; 390
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408 case AlphaISA::IPR_SIRR:
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391 case IPR_SIRR: |
392 // only write software interrupt mask 393 ipr[idx] = val & 0x7fff0; 394 break; 395
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413 case AlphaISA::IPR_ICSR:
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396 case IPR_ICSR: |
397 ipr[idx] = val & ULL(0xffffff0300); 398 break; 399
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417 case AlphaISA::IPR_IVPTBR:
418 case AlphaISA::IPR_MVPTBR:
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400 case IPR_IVPTBR: 401 case IPR_MVPTBR: |
402 ipr[idx] = val & ULL(0xffffffffc0000000); 403 break; 404
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422 case AlphaISA::IPR_DC_TEST_CTL:
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405 case IPR_DC_TEST_CTL: |
406 ipr[idx] = val & 0x1ffb; 407 break; 408
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426 case AlphaISA::IPR_DC_MODE:
427 case AlphaISA::IPR_MAF_MODE:
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409 case IPR_DC_MODE: 410 case IPR_MAF_MODE: |
411 ipr[idx] = val & 0x3f; 412 break; 413
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431 case AlphaISA::IPR_ITB_ASN:
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414 case IPR_ITB_ASN: |
415 ipr[idx] = val & 0x7f0; 416 break; 417
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435 case AlphaISA::IPR_DTB_ASN:
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418 case IPR_DTB_ASN: |
419 ipr[idx] = val & ULL(0xfe00000000000000); 420 break; 421
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439 case AlphaISA::IPR_EXC_SUM:
440 case AlphaISA::IPR_EXC_MASK:
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422 case IPR_EXC_SUM: 423 case IPR_EXC_MASK: |
424 // any write to this register clears it 425 ipr[idx] = 0; 426 break; 427
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445 case AlphaISA::IPR_INTID:
446 case AlphaISA::IPR_SL_RCV:
447 case AlphaISA::IPR_MM_STAT:
448 case AlphaISA::IPR_ITB_PTE_TEMP:
449 case AlphaISA::IPR_DTB_PTE_TEMP:
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428 case IPR_INTID: 429 case IPR_SL_RCV: 430 case IPR_MM_STAT: 431 case IPR_ITB_PTE_TEMP: 432 case IPR_DTB_PTE_TEMP: |
433 // read-only registers 434 panic("Tried to write read only ipr %d\n", idx); 435
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453 case AlphaISA::IPR_HWINT_CLR:
454 case AlphaISA::IPR_SL_XMIT:
455 case AlphaISA::IPR_DC_FLUSH:
456 case AlphaISA::IPR_IC_FLUSH:
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436 case IPR_HWINT_CLR: 437 case IPR_SL_XMIT: 438 case IPR_DC_FLUSH: 439 case IPR_IC_FLUSH: |
440 // the following are write only 441 ipr[idx] = val; 442 break; 443
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461 case AlphaISA::IPR_DTB_IA:
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444 case IPR_DTB_IA: |
445 // really a control write 446 ipr[idx] = 0; 447 448 tc->getDTBPtr()->flushAll(); 449 break; 450
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468 case AlphaISA::IPR_DTB_IAP:
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451 case IPR_DTB_IAP: |
452 // really a control write 453 ipr[idx] = 0; 454 455 tc->getDTBPtr()->flushProcesses(); 456 break; 457
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475 case AlphaISA::IPR_DTB_IS:
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458 case IPR_DTB_IS: |
459 // really a control write 460 ipr[idx] = val; 461 462 tc->getDTBPtr()->flushAddr(val,
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480 AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
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463 DTB_ASN_ASN(ipr[IPR_DTB_ASN])); |
464 break; 465
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483 case AlphaISA::IPR_DTB_TAG: {
484 struct AlphaISA::TlbEntry entry;
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466 case IPR_DTB_TAG: { 467 struct TlbEntry entry; |
468 469 // FIXME: granularity hints NYI...
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487 if (AlphaISA::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
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470 if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0) |
471 panic("PTE GH field != 0"); 472 473 // write entire quad 474 ipr[idx] = val; 475 476 // construct PTE for new entry
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494 entry.ppn = AlphaISA::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
495 entry.xre = AlphaISA::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
496 entry.xwe = AlphaISA::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
497 entry.fonr = AlphaISA::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
498 entry.fonw = AlphaISA::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
499 entry.asma = AlphaISA::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
500 entry.asn = AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
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477 entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]); 478 entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]); 479 entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]); 480 entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]); 481 entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]); 482 entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]); 483 entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]); |
484 485 // insert new TAG/PTE value into data TLB 486 tc->getDTBPtr()->insert(val, entry); 487 } 488 break; 489
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507 case AlphaISA::IPR_ITB_PTE: {
508 struct AlphaISA::TlbEntry entry;
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490 case IPR_ITB_PTE: { 491 struct TlbEntry entry; |
492 493 // FIXME: granularity hints NYI...
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511 if (AlphaISA::ITB_PTE_GH(val) != 0)
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494 if (ITB_PTE_GH(val) != 0) |
495 panic("PTE GH field != 0"); 496 497 // write entire quad 498 ipr[idx] = val; 499 500 // construct PTE for new entry
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518 entry.ppn = AlphaISA::ITB_PTE_PPN(val);
519 entry.xre = AlphaISA::ITB_PTE_XRE(val);
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501 entry.ppn = ITB_PTE_PPN(val); 502 entry.xre = ITB_PTE_XRE(val); |
503 entry.xwe = 0;
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521 entry.fonr = AlphaISA::ITB_PTE_FONR(val);
522 entry.fonw = AlphaISA::ITB_PTE_FONW(val);
523 entry.asma = AlphaISA::ITB_PTE_ASMA(val);
524 entry.asn = AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
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504 entry.fonr = ITB_PTE_FONR(val); 505 entry.fonw = ITB_PTE_FONW(val); 506 entry.asma = ITB_PTE_ASMA(val); 507 entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]); |
508 509 // insert new TAG/PTE value into data TLB
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527 tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], entry);
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510 tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry); |
511 } 512 break; 513
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531 case AlphaISA::IPR_ITB_IA:
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514 case IPR_ITB_IA: |
515 // really a control write 516 ipr[idx] = 0; 517 518 tc->getITBPtr()->flushAll(); 519 break; 520
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538 case AlphaISA::IPR_ITB_IAP:
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521 case IPR_ITB_IAP: |
522 // really a control write 523 ipr[idx] = 0; 524 525 tc->getITBPtr()->flushProcesses(); 526 break; 527
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545 case AlphaISA::IPR_ITB_IS:
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528 case IPR_ITB_IS: |
529 // really a control write 530 ipr[idx] = val; 531 532 tc->getITBPtr()->flushAddr(val,
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550 AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
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533 ITB_ASN_ASN(ipr[IPR_ITB_ASN])); |
534 break; 535 536 default: 537 // invalid IPR 538 panic("Tried to write to invalid ipr %d\n", idx); 539 } 540 541 // no error... 542} 543 544 545void
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563AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
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546copyIprs(ThreadContext *src, ThreadContext *dest) |
547{ 548 for (int i = 0; i < NumInternalProcRegs; ++i) { 549 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 550 } 551} 552
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553} // namespace AlphaISA 554 |
555#if FULL_SYSTEM
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556using namespace AlphaISA; |
557
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558Fault 559SimpleThread::hwrei() 560{ 561 if (!(readPC() & 0x3)) 562 return new UnimplementedOpcodeFault; 563 564 setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR)); 565 566 if (!misspeculating()) { 567 if (kernelStats) 568 kernelStats->hwrei(); 569 } 570 571 // FIXME: XXX check for interrupts? XXX 572 return NoFault; 573} 574 |
575/** 576 * Check for special simulator handling of specific PAL calls. 577 * If return value is false, actual PAL call will be suppressed. 578 */ 579bool 580SimpleThread::simPalCheck(int palFunc) 581{ 582 if (kernelStats) 583 kernelStats->callpal(palFunc, tc); 584 585 switch (palFunc) { 586 case PAL::halt: 587 halt(); 588 if (--System::numSystemsRunning == 0) 589 exitSimLoop("all cpus halted"); 590 break; 591 592 case PAL::bpt: 593 case PAL::bugchk: 594 if (system->breakpoint()) 595 return false; 596 break; 597 } 598 599 return true; 600} 601 602#endif // FULL_SYSTEM
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