1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 188 unchanged lines hidden (view full) --- 197} 198 199// Cause the simulator to break when changing to the following IPL 200int break_ipl = -1; 201 202void 203ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) 204{ |
205 if (tc->misspeculating()) 206 return; 207 208 switch (idx) { 209 case IPR_PALtemp0: 210 case IPR_PALtemp1: 211 case IPR_PALtemp2: 212 case IPR_PALtemp3: --- 35 unchanged lines hidden (view full) --- 248 // This IPR only writes the upper 64 bits. It's ok to write 249 // all 64 here since we mask out the lower 32 in rpcc (see 250 // isa_desc). 251 ipr[idx] = val; 252 break; 253 254 case IPR_PALtemp23: 255 // write entire quad w/ no side-effect |
256 if (tc->getKernelStats()) |
257 tc->getKernelStats()->context(ipr[idx], val, tc); 258 ipr[idx] = val; |
259 break; 260 261 case IPR_DTB_PTE: 262 // write entire quad w/ no side-effect, tag is forthcoming 263 ipr[idx] = val; 264 break; 265 266 case IPR_EXC_ADDR: --- 255 unchanged lines hidden --- |