1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 45 unchanged lines hidden (view full) --- 54void 55AlphaISA::initCPU(ThreadContext *tc, int cpuId) 56{ 57 initIPRs(tc, cpuId); 58 59 tc->setIntReg(16, cpuId); 60 tc->setIntReg(0, cpuId); 61 |
62 AlphaFault *reset = new ResetFault; 63 64 tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect()); |
65 tc->setNextPC(tc->readPC() + sizeof(MachInst)); |
66 67 delete reset; |
68} 69 70//////////////////////////////////////////////////////////////////////// 71// 72// 73// 74void 75AlphaISA::initIPRs(ThreadContext *tc, int cpuId) --- 516 unchanged lines hidden --- |