47c47
< using namespace AlphaISA;
---
> namespace AlphaISA {
56c56
< AlphaISA::initCPU(ThreadContext *tc, int cpuId)
---
> initCPU(ThreadContext *tc, int cpuId)
63c63
< AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
---
> AlphaFault *reset = new ResetFault;
74c74
< AlphaISA::processInterrupts(CPU *cpu)
---
> processInterrupts(CPU *cpu)
120c120
< AlphaISA::zeroRegisters(CPU *cpu)
---
> zeroRegisters(CPU *cpu)
129,145d128
< Fault
< SimpleThread::hwrei()
< {
< if (!(readPC() & 0x3))
< return new UnimplementedOpcodeFault;
<
< setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
<
< if (!misspeculating()) {
< if (kernelStats)
< kernelStats->hwrei();
< }
<
< // FIXME: XXX check for interrupts? XXX
< return NoFault;
< }
<
147c130
< AlphaISA::MiscRegFile::getInstAsid()
---
> MiscRegFile::getInstAsid()
149c132
< return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
---
> return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
153c136
< AlphaISA::MiscRegFile::getDataAsid()
---
> MiscRegFile::getDataAsid()
155c138
< return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
---
> return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
165c148
< AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
---
> initIPRs(ThreadContext *tc, int cpuId)
171c154
< tc->setMiscRegNoEffect(IPR_PAL_BASE, AlphaISA::PalBase);
---
> tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
176,177c159,160
< AlphaISA::MiscReg
< AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
---
> MiscReg
> MiscRegFile::readIpr(int idx, ThreadContext *tc)
182,206c165,189
< case AlphaISA::IPR_PALtemp0:
< case AlphaISA::IPR_PALtemp1:
< case AlphaISA::IPR_PALtemp2:
< case AlphaISA::IPR_PALtemp3:
< case AlphaISA::IPR_PALtemp4:
< case AlphaISA::IPR_PALtemp5:
< case AlphaISA::IPR_PALtemp6:
< case AlphaISA::IPR_PALtemp7:
< case AlphaISA::IPR_PALtemp8:
< case AlphaISA::IPR_PALtemp9:
< case AlphaISA::IPR_PALtemp10:
< case AlphaISA::IPR_PALtemp11:
< case AlphaISA::IPR_PALtemp12:
< case AlphaISA::IPR_PALtemp13:
< case AlphaISA::IPR_PALtemp14:
< case AlphaISA::IPR_PALtemp15:
< case AlphaISA::IPR_PALtemp16:
< case AlphaISA::IPR_PALtemp17:
< case AlphaISA::IPR_PALtemp18:
< case AlphaISA::IPR_PALtemp19:
< case AlphaISA::IPR_PALtemp20:
< case AlphaISA::IPR_PALtemp21:
< case AlphaISA::IPR_PALtemp22:
< case AlphaISA::IPR_PALtemp23:
< case AlphaISA::IPR_PAL_BASE:
---
> case IPR_PALtemp0:
> case IPR_PALtemp1:
> case IPR_PALtemp2:
> case IPR_PALtemp3:
> case IPR_PALtemp4:
> case IPR_PALtemp5:
> case IPR_PALtemp6:
> case IPR_PALtemp7:
> case IPR_PALtemp8:
> case IPR_PALtemp9:
> case IPR_PALtemp10:
> case IPR_PALtemp11:
> case IPR_PALtemp12:
> case IPR_PALtemp13:
> case IPR_PALtemp14:
> case IPR_PALtemp15:
> case IPR_PALtemp16:
> case IPR_PALtemp17:
> case IPR_PALtemp18:
> case IPR_PALtemp19:
> case IPR_PALtemp20:
> case IPR_PALtemp21:
> case IPR_PALtemp22:
> case IPR_PALtemp23:
> case IPR_PAL_BASE:
208,224c191,207
< case AlphaISA::IPR_IVPTBR:
< case AlphaISA::IPR_DC_MODE:
< case AlphaISA::IPR_MAF_MODE:
< case AlphaISA::IPR_ISR:
< case AlphaISA::IPR_EXC_ADDR:
< case AlphaISA::IPR_IC_PERR_STAT:
< case AlphaISA::IPR_DC_PERR_STAT:
< case AlphaISA::IPR_MCSR:
< case AlphaISA::IPR_ASTRR:
< case AlphaISA::IPR_ASTER:
< case AlphaISA::IPR_SIRR:
< case AlphaISA::IPR_ICSR:
< case AlphaISA::IPR_ICM:
< case AlphaISA::IPR_DTB_CM:
< case AlphaISA::IPR_IPLR:
< case AlphaISA::IPR_INTID:
< case AlphaISA::IPR_PMCTR:
---
> case IPR_IVPTBR:
> case IPR_DC_MODE:
> case IPR_MAF_MODE:
> case IPR_ISR:
> case IPR_EXC_ADDR:
> case IPR_IC_PERR_STAT:
> case IPR_DC_PERR_STAT:
> case IPR_MCSR:
> case IPR_ASTRR:
> case IPR_ASTER:
> case IPR_SIRR:
> case IPR_ICSR:
> case IPR_ICM:
> case IPR_DTB_CM:
> case IPR_IPLR:
> case IPR_INTID:
> case IPR_PMCTR:
229c212
< case AlphaISA::IPR_CC:
---
> case IPR_CC:
234c217
< case AlphaISA::IPR_VA:
---
> case IPR_VA:
238,242c221,225
< case AlphaISA::IPR_VA_FORM:
< case AlphaISA::IPR_MM_STAT:
< case AlphaISA::IPR_IFAULT_VA_FORM:
< case AlphaISA::IPR_EXC_MASK:
< case AlphaISA::IPR_EXC_SUM:
---
> case IPR_VA_FORM:
> case IPR_MM_STAT:
> case IPR_IFAULT_VA_FORM:
> case IPR_EXC_MASK:
> case IPR_EXC_SUM:
246c229
< case AlphaISA::IPR_DTB_PTE:
---
> case IPR_DTB_PTE:
248c231
< AlphaISA::TlbEntry &entry
---
> TlbEntry &entry
262,270c245,253
< case AlphaISA::IPR_HWINT_CLR:
< case AlphaISA::IPR_SL_XMIT:
< case AlphaISA::IPR_DC_FLUSH:
< case AlphaISA::IPR_IC_FLUSH:
< case AlphaISA::IPR_ALT_MODE:
< case AlphaISA::IPR_DTB_IA:
< case AlphaISA::IPR_DTB_IAP:
< case AlphaISA::IPR_ITB_IA:
< case AlphaISA::IPR_ITB_IAP:
---
> case IPR_HWINT_CLR:
> case IPR_SL_XMIT:
> case IPR_DC_FLUSH:
> case IPR_IC_FLUSH:
> case IPR_ALT_MODE:
> case IPR_DTB_IA:
> case IPR_DTB_IAP:
> case IPR_ITB_IA:
> case IPR_ITB_IAP:
289c272
< AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
---
> MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
297,323c280,306
< case AlphaISA::IPR_PALtemp0:
< case AlphaISA::IPR_PALtemp1:
< case AlphaISA::IPR_PALtemp2:
< case AlphaISA::IPR_PALtemp3:
< case AlphaISA::IPR_PALtemp4:
< case AlphaISA::IPR_PALtemp5:
< case AlphaISA::IPR_PALtemp6:
< case AlphaISA::IPR_PALtemp7:
< case AlphaISA::IPR_PALtemp8:
< case AlphaISA::IPR_PALtemp9:
< case AlphaISA::IPR_PALtemp10:
< case AlphaISA::IPR_PALtemp11:
< case AlphaISA::IPR_PALtemp12:
< case AlphaISA::IPR_PALtemp13:
< case AlphaISA::IPR_PALtemp14:
< case AlphaISA::IPR_PALtemp15:
< case AlphaISA::IPR_PALtemp16:
< case AlphaISA::IPR_PALtemp17:
< case AlphaISA::IPR_PALtemp18:
< case AlphaISA::IPR_PALtemp19:
< case AlphaISA::IPR_PALtemp20:
< case AlphaISA::IPR_PALtemp21:
< case AlphaISA::IPR_PALtemp22:
< case AlphaISA::IPR_PAL_BASE:
< case AlphaISA::IPR_IC_PERR_STAT:
< case AlphaISA::IPR_DC_PERR_STAT:
< case AlphaISA::IPR_PMCTR:
---
> case IPR_PALtemp0:
> case IPR_PALtemp1:
> case IPR_PALtemp2:
> case IPR_PALtemp3:
> case IPR_PALtemp4:
> case IPR_PALtemp5:
> case IPR_PALtemp6:
> case IPR_PALtemp7:
> case IPR_PALtemp8:
> case IPR_PALtemp9:
> case IPR_PALtemp10:
> case IPR_PALtemp11:
> case IPR_PALtemp12:
> case IPR_PALtemp13:
> case IPR_PALtemp14:
> case IPR_PALtemp15:
> case IPR_PALtemp16:
> case IPR_PALtemp17:
> case IPR_PALtemp18:
> case IPR_PALtemp19:
> case IPR_PALtemp20:
> case IPR_PALtemp21:
> case IPR_PALtemp22:
> case IPR_PAL_BASE:
> case IPR_IC_PERR_STAT:
> case IPR_DC_PERR_STAT:
> case IPR_PMCTR:
328c311
< case AlphaISA::IPR_CC_CTL:
---
> case IPR_CC_CTL:
335c318
< case AlphaISA::IPR_CC:
---
> case IPR_CC:
342c325
< case AlphaISA::IPR_PALtemp23:
---
> case IPR_PALtemp23:
352c335
< case AlphaISA::IPR_DTB_PTE:
---
> case IPR_DTB_PTE:
357c340
< case AlphaISA::IPR_EXC_ADDR:
---
> case IPR_EXC_ADDR:
362,363c345,346
< case AlphaISA::IPR_ASTRR:
< case AlphaISA::IPR_ASTER:
---
> case IPR_ASTRR:
> case IPR_ASTER:
368c351
< case AlphaISA::IPR_IPLR:
---
> case IPR_IPLR:
382c365
< case AlphaISA::IPR_DTB_CM:
---
> case IPR_DTB_CM:
386c369
< tc->getKernelStats()->mode(AlphaISA::Kernel::user, tc);
---
> tc->getKernelStats()->mode(Kernel::user, tc);
389c372
< tc->getKernelStats()->mode(AlphaISA::Kernel::kernel, tc);
---
> tc->getKernelStats()->mode(Kernel::kernel, tc);
393c376
< case AlphaISA::IPR_ICM:
---
> case IPR_ICM:
398c381
< case AlphaISA::IPR_ALT_MODE:
---
> case IPR_ALT_MODE:
403c386
< case AlphaISA::IPR_MCSR:
---
> case IPR_MCSR:
408c391
< case AlphaISA::IPR_SIRR:
---
> case IPR_SIRR:
413c396
< case AlphaISA::IPR_ICSR:
---
> case IPR_ICSR:
417,418c400,401
< case AlphaISA::IPR_IVPTBR:
< case AlphaISA::IPR_MVPTBR:
---
> case IPR_IVPTBR:
> case IPR_MVPTBR:
422c405
< case AlphaISA::IPR_DC_TEST_CTL:
---
> case IPR_DC_TEST_CTL:
426,427c409,410
< case AlphaISA::IPR_DC_MODE:
< case AlphaISA::IPR_MAF_MODE:
---
> case IPR_DC_MODE:
> case IPR_MAF_MODE:
431c414
< case AlphaISA::IPR_ITB_ASN:
---
> case IPR_ITB_ASN:
435c418
< case AlphaISA::IPR_DTB_ASN:
---
> case IPR_DTB_ASN:
439,440c422,423
< case AlphaISA::IPR_EXC_SUM:
< case AlphaISA::IPR_EXC_MASK:
---
> case IPR_EXC_SUM:
> case IPR_EXC_MASK:
445,449c428,432
< case AlphaISA::IPR_INTID:
< case AlphaISA::IPR_SL_RCV:
< case AlphaISA::IPR_MM_STAT:
< case AlphaISA::IPR_ITB_PTE_TEMP:
< case AlphaISA::IPR_DTB_PTE_TEMP:
---
> case IPR_INTID:
> case IPR_SL_RCV:
> case IPR_MM_STAT:
> case IPR_ITB_PTE_TEMP:
> case IPR_DTB_PTE_TEMP:
453,456c436,439
< case AlphaISA::IPR_HWINT_CLR:
< case AlphaISA::IPR_SL_XMIT:
< case AlphaISA::IPR_DC_FLUSH:
< case AlphaISA::IPR_IC_FLUSH:
---
> case IPR_HWINT_CLR:
> case IPR_SL_XMIT:
> case IPR_DC_FLUSH:
> case IPR_IC_FLUSH:
461c444
< case AlphaISA::IPR_DTB_IA:
---
> case IPR_DTB_IA:
468c451
< case AlphaISA::IPR_DTB_IAP:
---
> case IPR_DTB_IAP:
475c458
< case AlphaISA::IPR_DTB_IS:
---
> case IPR_DTB_IS:
480c463
< AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
---
> DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
483,484c466,467
< case AlphaISA::IPR_DTB_TAG: {
< struct AlphaISA::TlbEntry entry;
---
> case IPR_DTB_TAG: {
> struct TlbEntry entry;
487c470
< if (AlphaISA::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
---
> if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
494,500c477,483
< entry.ppn = AlphaISA::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
< entry.xre = AlphaISA::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
< entry.xwe = AlphaISA::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
< entry.fonr = AlphaISA::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
< entry.fonw = AlphaISA::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
< entry.asma = AlphaISA::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
< entry.asn = AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
---
> entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]);
> entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]);
> entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]);
> entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]);
> entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]);
> entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]);
> entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
507,508c490,491
< case AlphaISA::IPR_ITB_PTE: {
< struct AlphaISA::TlbEntry entry;
---
> case IPR_ITB_PTE: {
> struct TlbEntry entry;
511c494
< if (AlphaISA::ITB_PTE_GH(val) != 0)
---
> if (ITB_PTE_GH(val) != 0)
518,519c501,502
< entry.ppn = AlphaISA::ITB_PTE_PPN(val);
< entry.xre = AlphaISA::ITB_PTE_XRE(val);
---
> entry.ppn = ITB_PTE_PPN(val);
> entry.xre = ITB_PTE_XRE(val);
521,524c504,507
< entry.fonr = AlphaISA::ITB_PTE_FONR(val);
< entry.fonw = AlphaISA::ITB_PTE_FONW(val);
< entry.asma = AlphaISA::ITB_PTE_ASMA(val);
< entry.asn = AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
---
> entry.fonr = ITB_PTE_FONR(val);
> entry.fonw = ITB_PTE_FONW(val);
> entry.asma = ITB_PTE_ASMA(val);
> entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
527c510
< tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], entry);
---
> tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry);
531c514
< case AlphaISA::IPR_ITB_IA:
---
> case IPR_ITB_IA:
538c521
< case AlphaISA::IPR_ITB_IAP:
---
> case IPR_ITB_IAP:
545c528
< case AlphaISA::IPR_ITB_IS:
---
> case IPR_ITB_IS:
550c533
< AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
---
> ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
563c546
< AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
---
> copyIprs(ThreadContext *src, ThreadContext *dest)
569a553,554
> } // namespace AlphaISA
>
570a556
> using namespace AlphaISA;
571a558,574
> Fault
> SimpleThread::hwrei()
> {
> if (!(readPC() & 0x3))
> return new UnimplementedOpcodeFault;
>
> setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
>
> if (!misspeculating()) {
> if (kernelStats)
> kernelStats->hwrei();
> }
>
> // FIXME: XXX check for interrupts? XXX
> return NoFault;
> }
>
< using namespace AlphaISA;
---
> namespace AlphaISA {
56c56
< AlphaISA::initCPU(ThreadContext *tc, int cpuId)
---
> initCPU(ThreadContext *tc, int cpuId)
63c63
< AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
---
> AlphaFault *reset = new ResetFault;
74c74
< AlphaISA::processInterrupts(CPU *cpu)
---
> processInterrupts(CPU *cpu)
120c120
< AlphaISA::zeroRegisters(CPU *cpu)
---
> zeroRegisters(CPU *cpu)
129,145d128
< Fault
< SimpleThread::hwrei()
< {
< if (!(readPC() & 0x3))
< return new UnimplementedOpcodeFault;
<
< setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
<
< if (!misspeculating()) {
< if (kernelStats)
< kernelStats->hwrei();
< }
<
< // FIXME: XXX check for interrupts? XXX
< return NoFault;
< }
<
147c130
< AlphaISA::MiscRegFile::getInstAsid()
---
> MiscRegFile::getInstAsid()
149c132
< return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
---
> return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
153c136
< AlphaISA::MiscRegFile::getDataAsid()
---
> MiscRegFile::getDataAsid()
155c138
< return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
---
> return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
165c148
< AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
---
> initIPRs(ThreadContext *tc, int cpuId)
171c154
< tc->setMiscRegNoEffect(IPR_PAL_BASE, AlphaISA::PalBase);
---
> tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
176,177c159,160
< AlphaISA::MiscReg
< AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
---
> MiscReg
> MiscRegFile::readIpr(int idx, ThreadContext *tc)
182,206c165,189
< case AlphaISA::IPR_PALtemp0:
< case AlphaISA::IPR_PALtemp1:
< case AlphaISA::IPR_PALtemp2:
< case AlphaISA::IPR_PALtemp3:
< case AlphaISA::IPR_PALtemp4:
< case AlphaISA::IPR_PALtemp5:
< case AlphaISA::IPR_PALtemp6:
< case AlphaISA::IPR_PALtemp7:
< case AlphaISA::IPR_PALtemp8:
< case AlphaISA::IPR_PALtemp9:
< case AlphaISA::IPR_PALtemp10:
< case AlphaISA::IPR_PALtemp11:
< case AlphaISA::IPR_PALtemp12:
< case AlphaISA::IPR_PALtemp13:
< case AlphaISA::IPR_PALtemp14:
< case AlphaISA::IPR_PALtemp15:
< case AlphaISA::IPR_PALtemp16:
< case AlphaISA::IPR_PALtemp17:
< case AlphaISA::IPR_PALtemp18:
< case AlphaISA::IPR_PALtemp19:
< case AlphaISA::IPR_PALtemp20:
< case AlphaISA::IPR_PALtemp21:
< case AlphaISA::IPR_PALtemp22:
< case AlphaISA::IPR_PALtemp23:
< case AlphaISA::IPR_PAL_BASE:
---
> case IPR_PALtemp0:
> case IPR_PALtemp1:
> case IPR_PALtemp2:
> case IPR_PALtemp3:
> case IPR_PALtemp4:
> case IPR_PALtemp5:
> case IPR_PALtemp6:
> case IPR_PALtemp7:
> case IPR_PALtemp8:
> case IPR_PALtemp9:
> case IPR_PALtemp10:
> case IPR_PALtemp11:
> case IPR_PALtemp12:
> case IPR_PALtemp13:
> case IPR_PALtemp14:
> case IPR_PALtemp15:
> case IPR_PALtemp16:
> case IPR_PALtemp17:
> case IPR_PALtemp18:
> case IPR_PALtemp19:
> case IPR_PALtemp20:
> case IPR_PALtemp21:
> case IPR_PALtemp22:
> case IPR_PALtemp23:
> case IPR_PAL_BASE:
208,224c191,207
< case AlphaISA::IPR_IVPTBR:
< case AlphaISA::IPR_DC_MODE:
< case AlphaISA::IPR_MAF_MODE:
< case AlphaISA::IPR_ISR:
< case AlphaISA::IPR_EXC_ADDR:
< case AlphaISA::IPR_IC_PERR_STAT:
< case AlphaISA::IPR_DC_PERR_STAT:
< case AlphaISA::IPR_MCSR:
< case AlphaISA::IPR_ASTRR:
< case AlphaISA::IPR_ASTER:
< case AlphaISA::IPR_SIRR:
< case AlphaISA::IPR_ICSR:
< case AlphaISA::IPR_ICM:
< case AlphaISA::IPR_DTB_CM:
< case AlphaISA::IPR_IPLR:
< case AlphaISA::IPR_INTID:
< case AlphaISA::IPR_PMCTR:
---
> case IPR_IVPTBR:
> case IPR_DC_MODE:
> case IPR_MAF_MODE:
> case IPR_ISR:
> case IPR_EXC_ADDR:
> case IPR_IC_PERR_STAT:
> case IPR_DC_PERR_STAT:
> case IPR_MCSR:
> case IPR_ASTRR:
> case IPR_ASTER:
> case IPR_SIRR:
> case IPR_ICSR:
> case IPR_ICM:
> case IPR_DTB_CM:
> case IPR_IPLR:
> case IPR_INTID:
> case IPR_PMCTR:
229c212
< case AlphaISA::IPR_CC:
---
> case IPR_CC:
234c217
< case AlphaISA::IPR_VA:
---
> case IPR_VA:
238,242c221,225
< case AlphaISA::IPR_VA_FORM:
< case AlphaISA::IPR_MM_STAT:
< case AlphaISA::IPR_IFAULT_VA_FORM:
< case AlphaISA::IPR_EXC_MASK:
< case AlphaISA::IPR_EXC_SUM:
---
> case IPR_VA_FORM:
> case IPR_MM_STAT:
> case IPR_IFAULT_VA_FORM:
> case IPR_EXC_MASK:
> case IPR_EXC_SUM:
246c229
< case AlphaISA::IPR_DTB_PTE:
---
> case IPR_DTB_PTE:
248c231
< AlphaISA::TlbEntry &entry
---
> TlbEntry &entry
262,270c245,253
< case AlphaISA::IPR_HWINT_CLR:
< case AlphaISA::IPR_SL_XMIT:
< case AlphaISA::IPR_DC_FLUSH:
< case AlphaISA::IPR_IC_FLUSH:
< case AlphaISA::IPR_ALT_MODE:
< case AlphaISA::IPR_DTB_IA:
< case AlphaISA::IPR_DTB_IAP:
< case AlphaISA::IPR_ITB_IA:
< case AlphaISA::IPR_ITB_IAP:
---
> case IPR_HWINT_CLR:
> case IPR_SL_XMIT:
> case IPR_DC_FLUSH:
> case IPR_IC_FLUSH:
> case IPR_ALT_MODE:
> case IPR_DTB_IA:
> case IPR_DTB_IAP:
> case IPR_ITB_IA:
> case IPR_ITB_IAP:
289c272
< AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
---
> MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
297,323c280,306
< case AlphaISA::IPR_PALtemp0:
< case AlphaISA::IPR_PALtemp1:
< case AlphaISA::IPR_PALtemp2:
< case AlphaISA::IPR_PALtemp3:
< case AlphaISA::IPR_PALtemp4:
< case AlphaISA::IPR_PALtemp5:
< case AlphaISA::IPR_PALtemp6:
< case AlphaISA::IPR_PALtemp7:
< case AlphaISA::IPR_PALtemp8:
< case AlphaISA::IPR_PALtemp9:
< case AlphaISA::IPR_PALtemp10:
< case AlphaISA::IPR_PALtemp11:
< case AlphaISA::IPR_PALtemp12:
< case AlphaISA::IPR_PALtemp13:
< case AlphaISA::IPR_PALtemp14:
< case AlphaISA::IPR_PALtemp15:
< case AlphaISA::IPR_PALtemp16:
< case AlphaISA::IPR_PALtemp17:
< case AlphaISA::IPR_PALtemp18:
< case AlphaISA::IPR_PALtemp19:
< case AlphaISA::IPR_PALtemp20:
< case AlphaISA::IPR_PALtemp21:
< case AlphaISA::IPR_PALtemp22:
< case AlphaISA::IPR_PAL_BASE:
< case AlphaISA::IPR_IC_PERR_STAT:
< case AlphaISA::IPR_DC_PERR_STAT:
< case AlphaISA::IPR_PMCTR:
---
> case IPR_PALtemp0:
> case IPR_PALtemp1:
> case IPR_PALtemp2:
> case IPR_PALtemp3:
> case IPR_PALtemp4:
> case IPR_PALtemp5:
> case IPR_PALtemp6:
> case IPR_PALtemp7:
> case IPR_PALtemp8:
> case IPR_PALtemp9:
> case IPR_PALtemp10:
> case IPR_PALtemp11:
> case IPR_PALtemp12:
> case IPR_PALtemp13:
> case IPR_PALtemp14:
> case IPR_PALtemp15:
> case IPR_PALtemp16:
> case IPR_PALtemp17:
> case IPR_PALtemp18:
> case IPR_PALtemp19:
> case IPR_PALtemp20:
> case IPR_PALtemp21:
> case IPR_PALtemp22:
> case IPR_PAL_BASE:
> case IPR_IC_PERR_STAT:
> case IPR_DC_PERR_STAT:
> case IPR_PMCTR:
328c311
< case AlphaISA::IPR_CC_CTL:
---
> case IPR_CC_CTL:
335c318
< case AlphaISA::IPR_CC:
---
> case IPR_CC:
342c325
< case AlphaISA::IPR_PALtemp23:
---
> case IPR_PALtemp23:
352c335
< case AlphaISA::IPR_DTB_PTE:
---
> case IPR_DTB_PTE:
357c340
< case AlphaISA::IPR_EXC_ADDR:
---
> case IPR_EXC_ADDR:
362,363c345,346
< case AlphaISA::IPR_ASTRR:
< case AlphaISA::IPR_ASTER:
---
> case IPR_ASTRR:
> case IPR_ASTER:
368c351
< case AlphaISA::IPR_IPLR:
---
> case IPR_IPLR:
382c365
< case AlphaISA::IPR_DTB_CM:
---
> case IPR_DTB_CM:
386c369
< tc->getKernelStats()->mode(AlphaISA::Kernel::user, tc);
---
> tc->getKernelStats()->mode(Kernel::user, tc);
389c372
< tc->getKernelStats()->mode(AlphaISA::Kernel::kernel, tc);
---
> tc->getKernelStats()->mode(Kernel::kernel, tc);
393c376
< case AlphaISA::IPR_ICM:
---
> case IPR_ICM:
398c381
< case AlphaISA::IPR_ALT_MODE:
---
> case IPR_ALT_MODE:
403c386
< case AlphaISA::IPR_MCSR:
---
> case IPR_MCSR:
408c391
< case AlphaISA::IPR_SIRR:
---
> case IPR_SIRR:
413c396
< case AlphaISA::IPR_ICSR:
---
> case IPR_ICSR:
417,418c400,401
< case AlphaISA::IPR_IVPTBR:
< case AlphaISA::IPR_MVPTBR:
---
> case IPR_IVPTBR:
> case IPR_MVPTBR:
422c405
< case AlphaISA::IPR_DC_TEST_CTL:
---
> case IPR_DC_TEST_CTL:
426,427c409,410
< case AlphaISA::IPR_DC_MODE:
< case AlphaISA::IPR_MAF_MODE:
---
> case IPR_DC_MODE:
> case IPR_MAF_MODE:
431c414
< case AlphaISA::IPR_ITB_ASN:
---
> case IPR_ITB_ASN:
435c418
< case AlphaISA::IPR_DTB_ASN:
---
> case IPR_DTB_ASN:
439,440c422,423
< case AlphaISA::IPR_EXC_SUM:
< case AlphaISA::IPR_EXC_MASK:
---
> case IPR_EXC_SUM:
> case IPR_EXC_MASK:
445,449c428,432
< case AlphaISA::IPR_INTID:
< case AlphaISA::IPR_SL_RCV:
< case AlphaISA::IPR_MM_STAT:
< case AlphaISA::IPR_ITB_PTE_TEMP:
< case AlphaISA::IPR_DTB_PTE_TEMP:
---
> case IPR_INTID:
> case IPR_SL_RCV:
> case IPR_MM_STAT:
> case IPR_ITB_PTE_TEMP:
> case IPR_DTB_PTE_TEMP:
453,456c436,439
< case AlphaISA::IPR_HWINT_CLR:
< case AlphaISA::IPR_SL_XMIT:
< case AlphaISA::IPR_DC_FLUSH:
< case AlphaISA::IPR_IC_FLUSH:
---
> case IPR_HWINT_CLR:
> case IPR_SL_XMIT:
> case IPR_DC_FLUSH:
> case IPR_IC_FLUSH:
461c444
< case AlphaISA::IPR_DTB_IA:
---
> case IPR_DTB_IA:
468c451
< case AlphaISA::IPR_DTB_IAP:
---
> case IPR_DTB_IAP:
475c458
< case AlphaISA::IPR_DTB_IS:
---
> case IPR_DTB_IS:
480c463
< AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
---
> DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
483,484c466,467
< case AlphaISA::IPR_DTB_TAG: {
< struct AlphaISA::TlbEntry entry;
---
> case IPR_DTB_TAG: {
> struct TlbEntry entry;
487c470
< if (AlphaISA::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
---
> if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
494,500c477,483
< entry.ppn = AlphaISA::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
< entry.xre = AlphaISA::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
< entry.xwe = AlphaISA::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
< entry.fonr = AlphaISA::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
< entry.fonw = AlphaISA::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
< entry.asma = AlphaISA::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
< entry.asn = AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
---
> entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]);
> entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]);
> entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]);
> entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]);
> entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]);
> entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]);
> entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
507,508c490,491
< case AlphaISA::IPR_ITB_PTE: {
< struct AlphaISA::TlbEntry entry;
---
> case IPR_ITB_PTE: {
> struct TlbEntry entry;
511c494
< if (AlphaISA::ITB_PTE_GH(val) != 0)
---
> if (ITB_PTE_GH(val) != 0)
518,519c501,502
< entry.ppn = AlphaISA::ITB_PTE_PPN(val);
< entry.xre = AlphaISA::ITB_PTE_XRE(val);
---
> entry.ppn = ITB_PTE_PPN(val);
> entry.xre = ITB_PTE_XRE(val);
521,524c504,507
< entry.fonr = AlphaISA::ITB_PTE_FONR(val);
< entry.fonw = AlphaISA::ITB_PTE_FONW(val);
< entry.asma = AlphaISA::ITB_PTE_ASMA(val);
< entry.asn = AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
---
> entry.fonr = ITB_PTE_FONR(val);
> entry.fonw = ITB_PTE_FONW(val);
> entry.asma = ITB_PTE_ASMA(val);
> entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
527c510
< tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], entry);
---
> tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry);
531c514
< case AlphaISA::IPR_ITB_IA:
---
> case IPR_ITB_IA:
538c521
< case AlphaISA::IPR_ITB_IAP:
---
> case IPR_ITB_IAP:
545c528
< case AlphaISA::IPR_ITB_IS:
---
> case IPR_ITB_IS:
550c533
< AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
---
> ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
563c546
< AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
---
> copyIprs(ThreadContext *src, ThreadContext *dest)
569a553,554
> } // namespace AlphaISA
>
570a556
> using namespace AlphaISA;
571a558,574
> Fault
> SimpleThread::hwrei()
> {
> if (!(readPC() & 0x3))
> return new UnimplementedOpcodeFault;
>
> setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
>
> if (!misspeculating()) {
> if (kernelStats)
> kernelStats->hwrei();
> }
>
> // FIXME: XXX check for interrupts? XXX
> return NoFault;
> }
>