1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#include "arch/alpha/faults.hh"
33#include "arch/alpha/isa_traits.hh"
34#include "arch/alpha/kernel_stats.hh"
35#include "arch/alpha/osfpal.hh"
36#include "arch/alpha/tlb.hh"
37#include "arch/alpha/kgdb.h"
38#include "base/cp_annotate.hh"
39#include "base/debug.hh"
40#include "base/remote_gdb.hh"
41#include "base/stats/events.hh"
42#include "config/full_system.hh"
43#include "cpu/base.hh"
44#include "cpu/simple_thread.hh"
45#include "cpu/thread_context.hh"
46#include "sim/sim_exit.hh"
47
48namespace AlphaISA {
49
50#if FULL_SYSTEM
51
52////////////////////////////////////////////////////////////////////////
53//
54// Machine dependent functions
55//
56void
57initCPU(ThreadContext *tc, int cpuId)
58{
59 initIPRs(tc, cpuId);
60
61 tc->setIntReg(16, cpuId);
62 tc->setIntReg(0, cpuId);
63
64 AlphaFault *reset = new ResetFault;
65
66 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
67 tc->setNextPC(tc->readPC() + sizeof(MachInst));
68
69 delete reset;
70}
71
72
73template <class CPU>
74void
75processInterrupts(CPU *cpu)
76{
77 //Check if there are any outstanding interrupts
78 //Handle the interrupts
79 int ipl = 0;
80 int summary = 0;
81
82 if (cpu->readMiscRegNoEffect(IPR_ASTRR))
83 panic("asynchronous traps not implemented\n");
84
85 if (cpu->readMiscRegNoEffect(IPR_SIRR)) {
86 for (int i = INTLEVEL_SOFTWARE_MIN;
87 i < INTLEVEL_SOFTWARE_MAX; i++) {
88 if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
89 // See table 4-19 of the 21164 hardware reference
90 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
91 summary |= (ULL(1) << i);
92 }
93 }
94 }
95
96 uint64_t interrupts = cpu->intr_status();
97
98 if (interrupts) {
99 for (int i = INTLEVEL_EXTERNAL_MIN;
100 i < INTLEVEL_EXTERNAL_MAX; i++) {
101 if (interrupts & (ULL(1) << i)) {
102 // See table 4-19 of the 21164 hardware reference
103 ipl = i;
104 summary |= (ULL(1) << i);
105 }
106 }
107 }
108
109 if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) {
110 cpu->setMiscRegNoEffect(IPR_ISR, summary);
111 cpu->setMiscRegNoEffect(IPR_INTID, ipl);
112 cpu->trap(new InterruptFault);
113 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
114 cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
115 }
116
117}
118
119template <class CPU>
120void
121zeroRegisters(CPU *cpu)
122{
123 // Insure ISA semantics
124 // (no longer very clean due to the change in setIntReg() in the
125 // cpu model. Consider changing later.)
126 cpu->thread->setIntReg(ZeroReg, 0);
127 cpu->thread->setFloatReg(ZeroReg, 0.0);
128}
129
130int
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#include "arch/alpha/faults.hh"
33#include "arch/alpha/isa_traits.hh"
34#include "arch/alpha/kernel_stats.hh"
35#include "arch/alpha/osfpal.hh"
36#include "arch/alpha/tlb.hh"
37#include "arch/alpha/kgdb.h"
38#include "base/cp_annotate.hh"
39#include "base/debug.hh"
40#include "base/remote_gdb.hh"
41#include "base/stats/events.hh"
42#include "config/full_system.hh"
43#include "cpu/base.hh"
44#include "cpu/simple_thread.hh"
45#include "cpu/thread_context.hh"
46#include "sim/sim_exit.hh"
47
48namespace AlphaISA {
49
50#if FULL_SYSTEM
51
52////////////////////////////////////////////////////////////////////////
53//
54// Machine dependent functions
55//
56void
57initCPU(ThreadContext *tc, int cpuId)
58{
59 initIPRs(tc, cpuId);
60
61 tc->setIntReg(16, cpuId);
62 tc->setIntReg(0, cpuId);
63
64 AlphaFault *reset = new ResetFault;
65
66 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
67 tc->setNextPC(tc->readPC() + sizeof(MachInst));
68
69 delete reset;
70}
71
72
73template <class CPU>
74void
75processInterrupts(CPU *cpu)
76{
77 //Check if there are any outstanding interrupts
78 //Handle the interrupts
79 int ipl = 0;
80 int summary = 0;
81
82 if (cpu->readMiscRegNoEffect(IPR_ASTRR))
83 panic("asynchronous traps not implemented\n");
84
85 if (cpu->readMiscRegNoEffect(IPR_SIRR)) {
86 for (int i = INTLEVEL_SOFTWARE_MIN;
87 i < INTLEVEL_SOFTWARE_MAX; i++) {
88 if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
89 // See table 4-19 of the 21164 hardware reference
90 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
91 summary |= (ULL(1) << i);
92 }
93 }
94 }
95
96 uint64_t interrupts = cpu->intr_status();
97
98 if (interrupts) {
99 for (int i = INTLEVEL_EXTERNAL_MIN;
100 i < INTLEVEL_EXTERNAL_MAX; i++) {
101 if (interrupts & (ULL(1) << i)) {
102 // See table 4-19 of the 21164 hardware reference
103 ipl = i;
104 summary |= (ULL(1) << i);
105 }
106 }
107 }
108
109 if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) {
110 cpu->setMiscRegNoEffect(IPR_ISR, summary);
111 cpu->setMiscRegNoEffect(IPR_INTID, ipl);
112 cpu->trap(new InterruptFault);
113 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
114 cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
115 }
116
117}
118
119template <class CPU>
120void
121zeroRegisters(CPU *cpu)
122{
123 // Insure ISA semantics
124 // (no longer very clean due to the change in setIntReg() in the
125 // cpu model. Consider changing later.)
126 cpu->thread->setIntReg(ZeroReg, 0);
127 cpu->thread->setFloatReg(ZeroReg, 0.0);
128}
129
130int
|
131MiscRegFile::getInstAsid()
| 131ISA::getInstAsid()
|
132{
133 return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
134}
135
136int
| 132{
133 return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
134}
135
136int
|
137MiscRegFile::getDataAsid()
| 137ISA::getDataAsid()
|
138{
139 return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
140}
141
142#endif
143
144////////////////////////////////////////////////////////////////////////
145//
146//
147//
148void
149initIPRs(ThreadContext *tc, int cpuId)
150{
151 for (int i = 0; i < NumInternalProcRegs; ++i) {
152 tc->setMiscRegNoEffect(i, 0);
153 }
154
155 tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
156 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
157 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
158}
159
160MiscReg
| 138{
139 return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
140}
141
142#endif
143
144////////////////////////////////////////////////////////////////////////
145//
146//
147//
148void
149initIPRs(ThreadContext *tc, int cpuId)
150{
151 for (int i = 0; i < NumInternalProcRegs; ++i) {
152 tc->setMiscRegNoEffect(i, 0);
153 }
154
155 tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
156 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
157 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
158}
159
160MiscReg
|
161MiscRegFile::readIpr(int idx, ThreadContext *tc)
| 161ISA::readIpr(int idx, ThreadContext *tc)
|
162{
163 uint64_t retval = 0; // return value, default 0
164
165 switch (idx) {
166 case IPR_PALtemp0:
167 case IPR_PALtemp1:
168 case IPR_PALtemp2:
169 case IPR_PALtemp3:
170 case IPR_PALtemp4:
171 case IPR_PALtemp5:
172 case IPR_PALtemp6:
173 case IPR_PALtemp7:
174 case IPR_PALtemp8:
175 case IPR_PALtemp9:
176 case IPR_PALtemp10:
177 case IPR_PALtemp11:
178 case IPR_PALtemp12:
179 case IPR_PALtemp13:
180 case IPR_PALtemp14:
181 case IPR_PALtemp15:
182 case IPR_PALtemp16:
183 case IPR_PALtemp17:
184 case IPR_PALtemp18:
185 case IPR_PALtemp19:
186 case IPR_PALtemp20:
187 case IPR_PALtemp21:
188 case IPR_PALtemp22:
189 case IPR_PALtemp23:
190 case IPR_PAL_BASE:
191
192 case IPR_IVPTBR:
193 case IPR_DC_MODE:
194 case IPR_MAF_MODE:
195 case IPR_ISR:
196 case IPR_EXC_ADDR:
197 case IPR_IC_PERR_STAT:
198 case IPR_DC_PERR_STAT:
199 case IPR_MCSR:
200 case IPR_ASTRR:
201 case IPR_ASTER:
202 case IPR_SIRR:
203 case IPR_ICSR:
204 case IPR_ICM:
205 case IPR_DTB_CM:
206 case IPR_IPLR:
207 case IPR_INTID:
208 case IPR_PMCTR:
209 // no side-effect
210 retval = ipr[idx];
211 break;
212
213 case IPR_CC:
214 retval |= ipr[idx] & ULL(0xffffffff00000000);
215 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
216 break;
217
218 case IPR_VA:
219 retval = ipr[idx];
220 break;
221
222 case IPR_VA_FORM:
223 case IPR_MM_STAT:
224 case IPR_IFAULT_VA_FORM:
225 case IPR_EXC_MASK:
226 case IPR_EXC_SUM:
227 retval = ipr[idx];
228 break;
229
230 case IPR_DTB_PTE:
231 {
232 TlbEntry &entry
233 = tc->getDTBPtr()->index(!tc->misspeculating());
234
235 retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
236 retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
237 retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12;
238 retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1;
239 retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2;
240 retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4;
241 retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57;
242 }
243 break;
244
245 // write only registers
246 case IPR_HWINT_CLR:
247 case IPR_SL_XMIT:
248 case IPR_DC_FLUSH:
249 case IPR_IC_FLUSH:
250 case IPR_ALT_MODE:
251 case IPR_DTB_IA:
252 case IPR_DTB_IAP:
253 case IPR_ITB_IA:
254 case IPR_ITB_IAP:
255 panic("Tried to read write only register %d\n", idx);
256 break;
257
258 default:
259 // invalid IPR
260 panic("Tried to read from invalid ipr %d\n", idx);
261 break;
262 }
263
264 return retval;
265}
266
267#ifdef DEBUG
268// Cause the simulator to break when changing to the following IPL
269int break_ipl = -1;
270#endif
271
272void
| 162{
163 uint64_t retval = 0; // return value, default 0
164
165 switch (idx) {
166 case IPR_PALtemp0:
167 case IPR_PALtemp1:
168 case IPR_PALtemp2:
169 case IPR_PALtemp3:
170 case IPR_PALtemp4:
171 case IPR_PALtemp5:
172 case IPR_PALtemp6:
173 case IPR_PALtemp7:
174 case IPR_PALtemp8:
175 case IPR_PALtemp9:
176 case IPR_PALtemp10:
177 case IPR_PALtemp11:
178 case IPR_PALtemp12:
179 case IPR_PALtemp13:
180 case IPR_PALtemp14:
181 case IPR_PALtemp15:
182 case IPR_PALtemp16:
183 case IPR_PALtemp17:
184 case IPR_PALtemp18:
185 case IPR_PALtemp19:
186 case IPR_PALtemp20:
187 case IPR_PALtemp21:
188 case IPR_PALtemp22:
189 case IPR_PALtemp23:
190 case IPR_PAL_BASE:
191
192 case IPR_IVPTBR:
193 case IPR_DC_MODE:
194 case IPR_MAF_MODE:
195 case IPR_ISR:
196 case IPR_EXC_ADDR:
197 case IPR_IC_PERR_STAT:
198 case IPR_DC_PERR_STAT:
199 case IPR_MCSR:
200 case IPR_ASTRR:
201 case IPR_ASTER:
202 case IPR_SIRR:
203 case IPR_ICSR:
204 case IPR_ICM:
205 case IPR_DTB_CM:
206 case IPR_IPLR:
207 case IPR_INTID:
208 case IPR_PMCTR:
209 // no side-effect
210 retval = ipr[idx];
211 break;
212
213 case IPR_CC:
214 retval |= ipr[idx] & ULL(0xffffffff00000000);
215 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
216 break;
217
218 case IPR_VA:
219 retval = ipr[idx];
220 break;
221
222 case IPR_VA_FORM:
223 case IPR_MM_STAT:
224 case IPR_IFAULT_VA_FORM:
225 case IPR_EXC_MASK:
226 case IPR_EXC_SUM:
227 retval = ipr[idx];
228 break;
229
230 case IPR_DTB_PTE:
231 {
232 TlbEntry &entry
233 = tc->getDTBPtr()->index(!tc->misspeculating());
234
235 retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
236 retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
237 retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12;
238 retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1;
239 retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2;
240 retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4;
241 retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57;
242 }
243 break;
244
245 // write only registers
246 case IPR_HWINT_CLR:
247 case IPR_SL_XMIT:
248 case IPR_DC_FLUSH:
249 case IPR_IC_FLUSH:
250 case IPR_ALT_MODE:
251 case IPR_DTB_IA:
252 case IPR_DTB_IAP:
253 case IPR_ITB_IA:
254 case IPR_ITB_IAP:
255 panic("Tried to read write only register %d\n", idx);
256 break;
257
258 default:
259 // invalid IPR
260 panic("Tried to read from invalid ipr %d\n", idx);
261 break;
262 }
263
264 return retval;
265}
266
267#ifdef DEBUG
268// Cause the simulator to break when changing to the following IPL
269int break_ipl = -1;
270#endif
271
272void
|
273MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
| 273ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
|
274{
275 uint64_t old;
276
277 if (tc->misspeculating())
278 return;
279
280 switch (idx) {
281 case IPR_PALtemp0:
282 case IPR_PALtemp1:
283 case IPR_PALtemp2:
284 case IPR_PALtemp3:
285 case IPR_PALtemp4:
286 case IPR_PALtemp5:
287 case IPR_PALtemp6:
288 case IPR_PALtemp7:
289 case IPR_PALtemp8:
290 case IPR_PALtemp9:
291 case IPR_PALtemp10:
292 case IPR_PALtemp11:
293 case IPR_PALtemp12:
294 case IPR_PALtemp13:
295 case IPR_PALtemp14:
296 case IPR_PALtemp15:
297 case IPR_PALtemp16:
298 case IPR_PALtemp17:
299 case IPR_PALtemp18:
300 case IPR_PALtemp19:
301 case IPR_PALtemp20:
302 case IPR_PALtemp21:
303 case IPR_PALtemp22:
304 case IPR_PAL_BASE:
305 case IPR_IC_PERR_STAT:
306 case IPR_DC_PERR_STAT:
307 case IPR_PMCTR:
308 // write entire quad w/ no side-effect
309 ipr[idx] = val;
310 break;
311
312 case IPR_CC_CTL:
313 // This IPR resets the cycle counter. We assume this only
314 // happens once... let's verify that.
315 assert(ipr[idx] == 0);
316 ipr[idx] = 1;
317 break;
318
319 case IPR_CC:
320 // This IPR only writes the upper 64 bits. It's ok to write
321 // all 64 here since we mask out the lower 32 in rpcc (see
322 // isa_desc).
323 ipr[idx] = val;
324 break;
325
326 case IPR_PALtemp23:
327 // write entire quad w/ no side-effect
328 old = ipr[idx];
329 ipr[idx] = val;
330#if FULL_SYSTEM
331 if (tc->getKernelStats())
332 tc->getKernelStats()->context(old, val, tc);
333#endif
334 break;
335
336 case IPR_DTB_PTE:
337 // write entire quad w/ no side-effect, tag is forthcoming
338 ipr[idx] = val;
339 break;
340
341 case IPR_EXC_ADDR:
342 // second least significant bit in PC is always zero
343 ipr[idx] = val & ~2;
344 break;
345
346 case IPR_ASTRR:
347 case IPR_ASTER:
348 // only write least significant four bits - privilege mask
349 ipr[idx] = val & 0xf;
350 break;
351
352 case IPR_IPLR:
353#ifdef DEBUG
354 if (break_ipl != -1 && break_ipl == (int)(val & 0x1f))
355 debug_break();
356#endif
357
358 // only write least significant five bits - interrupt level
359 ipr[idx] = val & 0x1f;
360#if FULL_SYSTEM
361 if (tc->getKernelStats())
362 tc->getKernelStats()->swpipl(ipr[idx]);
363#endif
364 break;
365
366 case IPR_DTB_CM:
367#if FULL_SYSTEM
368 if (val & 0x18) {
369 if (tc->getKernelStats())
370 tc->getKernelStats()->mode(Kernel::user, tc);
371 } else {
372 if (tc->getKernelStats())
373 tc->getKernelStats()->mode(Kernel::kernel, tc);
374 }
375#endif
376
377 case IPR_ICM:
378 // only write two mode bits - processor mode
379 ipr[idx] = val & 0x18;
380 break;
381
382 case IPR_ALT_MODE:
383 // only write two mode bits - processor mode
384 ipr[idx] = val & 0x18;
385 break;
386
387 case IPR_MCSR:
388 // more here after optimization...
389 ipr[idx] = val;
390 break;
391
392 case IPR_SIRR:
393 // only write software interrupt mask
394 ipr[idx] = val & 0x7fff0;
395 break;
396
397 case IPR_ICSR:
398 ipr[idx] = val & ULL(0xffffff0300);
399 break;
400
401 case IPR_IVPTBR:
402 case IPR_MVPTBR:
403 ipr[idx] = val & ULL(0xffffffffc0000000);
404 break;
405
406 case IPR_DC_TEST_CTL:
407 ipr[idx] = val & 0x1ffb;
408 break;
409
410 case IPR_DC_MODE:
411 case IPR_MAF_MODE:
412 ipr[idx] = val & 0x3f;
413 break;
414
415 case IPR_ITB_ASN:
416 ipr[idx] = val & 0x7f0;
417 break;
418
419 case IPR_DTB_ASN:
420 ipr[idx] = val & ULL(0xfe00000000000000);
421 break;
422
423 case IPR_EXC_SUM:
424 case IPR_EXC_MASK:
425 // any write to this register clears it
426 ipr[idx] = 0;
427 break;
428
429 case IPR_INTID:
430 case IPR_SL_RCV:
431 case IPR_MM_STAT:
432 case IPR_ITB_PTE_TEMP:
433 case IPR_DTB_PTE_TEMP:
434 // read-only registers
435 panic("Tried to write read only ipr %d\n", idx);
436
437 case IPR_HWINT_CLR:
438 case IPR_SL_XMIT:
439 case IPR_DC_FLUSH:
440 case IPR_IC_FLUSH:
441 // the following are write only
442 ipr[idx] = val;
443 break;
444
445 case IPR_DTB_IA:
446 // really a control write
447 ipr[idx] = 0;
448
449 tc->getDTBPtr()->flushAll();
450 break;
451
452 case IPR_DTB_IAP:
453 // really a control write
454 ipr[idx] = 0;
455
456 tc->getDTBPtr()->flushProcesses();
457 break;
458
459 case IPR_DTB_IS:
460 // really a control write
461 ipr[idx] = val;
462
463 tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
464 break;
465
466 case IPR_DTB_TAG: {
467 struct TlbEntry entry;
468
469 // FIXME: granularity hints NYI...
470 if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
471 panic("PTE GH field != 0");
472
473 // write entire quad
474 ipr[idx] = val;
475
476 // construct PTE for new entry
477 entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]);
478 entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]);
479 entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]);
480 entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]);
481 entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]);
482 entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]);
483 entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
484
485 // insert new TAG/PTE value into data TLB
486 tc->getDTBPtr()->insert(val, entry);
487 }
488 break;
489
490 case IPR_ITB_PTE: {
491 struct TlbEntry entry;
492
493 // FIXME: granularity hints NYI...
494 if (ITB_PTE_GH(val) != 0)
495 panic("PTE GH field != 0");
496
497 // write entire quad
498 ipr[idx] = val;
499
500 // construct PTE for new entry
501 entry.ppn = ITB_PTE_PPN(val);
502 entry.xre = ITB_PTE_XRE(val);
503 entry.xwe = 0;
504 entry.fonr = ITB_PTE_FONR(val);
505 entry.fonw = ITB_PTE_FONW(val);
506 entry.asma = ITB_PTE_ASMA(val);
507 entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
508
509 // insert new TAG/PTE value into data TLB
510 tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry);
511 }
512 break;
513
514 case IPR_ITB_IA:
515 // really a control write
516 ipr[idx] = 0;
517
518 tc->getITBPtr()->flushAll();
519 break;
520
521 case IPR_ITB_IAP:
522 // really a control write
523 ipr[idx] = 0;
524
525 tc->getITBPtr()->flushProcesses();
526 break;
527
528 case IPR_ITB_IS:
529 // really a control write
530 ipr[idx] = val;
531
532 tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
533 break;
534
535 default:
536 // invalid IPR
537 panic("Tried to write to invalid ipr %d\n", idx);
538 }
539
540 // no error...
541}
542
543void
544copyIprs(ThreadContext *src, ThreadContext *dest)
545{
546 for (int i = 0; i < NumInternalProcRegs; ++i)
547 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
548}
549
550} // namespace AlphaISA
551
552#if FULL_SYSTEM
553
554using namespace AlphaISA;
555
556Fault
557SimpleThread::hwrei()
558{
559 if (!(readPC() & 0x3))
560 return new UnimplementedOpcodeFault;
561
562 setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
563
564 CPA::cpa()->swAutoBegin(tc, readNextPC());
565
566 if (!misspeculating()) {
567 if (kernelStats)
568 kernelStats->hwrei();
569 }
570
571 // FIXME: XXX check for interrupts? XXX
572 return NoFault;
573}
574
575/**
576 * Check for special simulator handling of specific PAL calls.
577 * If return value is false, actual PAL call will be suppressed.
578 */
579bool
580SimpleThread::simPalCheck(int palFunc)
581{
582 if (kernelStats)
583 kernelStats->callpal(palFunc, tc);
584
585 switch (palFunc) {
586 case PAL::halt:
587 halt();
588 if (--System::numSystemsRunning == 0)
589 exitSimLoop("all cpus halted");
590 break;
591
592 case PAL::bpt:
593 case PAL::bugchk:
594 if (system->breakpoint())
595 return false;
596 break;
597 }
598
599 return true;
600}
601
602#endif // FULL_SYSTEM
| 274{
275 uint64_t old;
276
277 if (tc->misspeculating())
278 return;
279
280 switch (idx) {
281 case IPR_PALtemp0:
282 case IPR_PALtemp1:
283 case IPR_PALtemp2:
284 case IPR_PALtemp3:
285 case IPR_PALtemp4:
286 case IPR_PALtemp5:
287 case IPR_PALtemp6:
288 case IPR_PALtemp7:
289 case IPR_PALtemp8:
290 case IPR_PALtemp9:
291 case IPR_PALtemp10:
292 case IPR_PALtemp11:
293 case IPR_PALtemp12:
294 case IPR_PALtemp13:
295 case IPR_PALtemp14:
296 case IPR_PALtemp15:
297 case IPR_PALtemp16:
298 case IPR_PALtemp17:
299 case IPR_PALtemp18:
300 case IPR_PALtemp19:
301 case IPR_PALtemp20:
302 case IPR_PALtemp21:
303 case IPR_PALtemp22:
304 case IPR_PAL_BASE:
305 case IPR_IC_PERR_STAT:
306 case IPR_DC_PERR_STAT:
307 case IPR_PMCTR:
308 // write entire quad w/ no side-effect
309 ipr[idx] = val;
310 break;
311
312 case IPR_CC_CTL:
313 // This IPR resets the cycle counter. We assume this only
314 // happens once... let's verify that.
315 assert(ipr[idx] == 0);
316 ipr[idx] = 1;
317 break;
318
319 case IPR_CC:
320 // This IPR only writes the upper 64 bits. It's ok to write
321 // all 64 here since we mask out the lower 32 in rpcc (see
322 // isa_desc).
323 ipr[idx] = val;
324 break;
325
326 case IPR_PALtemp23:
327 // write entire quad w/ no side-effect
328 old = ipr[idx];
329 ipr[idx] = val;
330#if FULL_SYSTEM
331 if (tc->getKernelStats())
332 tc->getKernelStats()->context(old, val, tc);
333#endif
334 break;
335
336 case IPR_DTB_PTE:
337 // write entire quad w/ no side-effect, tag is forthcoming
338 ipr[idx] = val;
339 break;
340
341 case IPR_EXC_ADDR:
342 // second least significant bit in PC is always zero
343 ipr[idx] = val & ~2;
344 break;
345
346 case IPR_ASTRR:
347 case IPR_ASTER:
348 // only write least significant four bits - privilege mask
349 ipr[idx] = val & 0xf;
350 break;
351
352 case IPR_IPLR:
353#ifdef DEBUG
354 if (break_ipl != -1 && break_ipl == (int)(val & 0x1f))
355 debug_break();
356#endif
357
358 // only write least significant five bits - interrupt level
359 ipr[idx] = val & 0x1f;
360#if FULL_SYSTEM
361 if (tc->getKernelStats())
362 tc->getKernelStats()->swpipl(ipr[idx]);
363#endif
364 break;
365
366 case IPR_DTB_CM:
367#if FULL_SYSTEM
368 if (val & 0x18) {
369 if (tc->getKernelStats())
370 tc->getKernelStats()->mode(Kernel::user, tc);
371 } else {
372 if (tc->getKernelStats())
373 tc->getKernelStats()->mode(Kernel::kernel, tc);
374 }
375#endif
376
377 case IPR_ICM:
378 // only write two mode bits - processor mode
379 ipr[idx] = val & 0x18;
380 break;
381
382 case IPR_ALT_MODE:
383 // only write two mode bits - processor mode
384 ipr[idx] = val & 0x18;
385 break;
386
387 case IPR_MCSR:
388 // more here after optimization...
389 ipr[idx] = val;
390 break;
391
392 case IPR_SIRR:
393 // only write software interrupt mask
394 ipr[idx] = val & 0x7fff0;
395 break;
396
397 case IPR_ICSR:
398 ipr[idx] = val & ULL(0xffffff0300);
399 break;
400
401 case IPR_IVPTBR:
402 case IPR_MVPTBR:
403 ipr[idx] = val & ULL(0xffffffffc0000000);
404 break;
405
406 case IPR_DC_TEST_CTL:
407 ipr[idx] = val & 0x1ffb;
408 break;
409
410 case IPR_DC_MODE:
411 case IPR_MAF_MODE:
412 ipr[idx] = val & 0x3f;
413 break;
414
415 case IPR_ITB_ASN:
416 ipr[idx] = val & 0x7f0;
417 break;
418
419 case IPR_DTB_ASN:
420 ipr[idx] = val & ULL(0xfe00000000000000);
421 break;
422
423 case IPR_EXC_SUM:
424 case IPR_EXC_MASK:
425 // any write to this register clears it
426 ipr[idx] = 0;
427 break;
428
429 case IPR_INTID:
430 case IPR_SL_RCV:
431 case IPR_MM_STAT:
432 case IPR_ITB_PTE_TEMP:
433 case IPR_DTB_PTE_TEMP:
434 // read-only registers
435 panic("Tried to write read only ipr %d\n", idx);
436
437 case IPR_HWINT_CLR:
438 case IPR_SL_XMIT:
439 case IPR_DC_FLUSH:
440 case IPR_IC_FLUSH:
441 // the following are write only
442 ipr[idx] = val;
443 break;
444
445 case IPR_DTB_IA:
446 // really a control write
447 ipr[idx] = 0;
448
449 tc->getDTBPtr()->flushAll();
450 break;
451
452 case IPR_DTB_IAP:
453 // really a control write
454 ipr[idx] = 0;
455
456 tc->getDTBPtr()->flushProcesses();
457 break;
458
459 case IPR_DTB_IS:
460 // really a control write
461 ipr[idx] = val;
462
463 tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
464 break;
465
466 case IPR_DTB_TAG: {
467 struct TlbEntry entry;
468
469 // FIXME: granularity hints NYI...
470 if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
471 panic("PTE GH field != 0");
472
473 // write entire quad
474 ipr[idx] = val;
475
476 // construct PTE for new entry
477 entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]);
478 entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]);
479 entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]);
480 entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]);
481 entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]);
482 entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]);
483 entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
484
485 // insert new TAG/PTE value into data TLB
486 tc->getDTBPtr()->insert(val, entry);
487 }
488 break;
489
490 case IPR_ITB_PTE: {
491 struct TlbEntry entry;
492
493 // FIXME: granularity hints NYI...
494 if (ITB_PTE_GH(val) != 0)
495 panic("PTE GH field != 0");
496
497 // write entire quad
498 ipr[idx] = val;
499
500 // construct PTE for new entry
501 entry.ppn = ITB_PTE_PPN(val);
502 entry.xre = ITB_PTE_XRE(val);
503 entry.xwe = 0;
504 entry.fonr = ITB_PTE_FONR(val);
505 entry.fonw = ITB_PTE_FONW(val);
506 entry.asma = ITB_PTE_ASMA(val);
507 entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
508
509 // insert new TAG/PTE value into data TLB
510 tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry);
511 }
512 break;
513
514 case IPR_ITB_IA:
515 // really a control write
516 ipr[idx] = 0;
517
518 tc->getITBPtr()->flushAll();
519 break;
520
521 case IPR_ITB_IAP:
522 // really a control write
523 ipr[idx] = 0;
524
525 tc->getITBPtr()->flushProcesses();
526 break;
527
528 case IPR_ITB_IS:
529 // really a control write
530 ipr[idx] = val;
531
532 tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
533 break;
534
535 default:
536 // invalid IPR
537 panic("Tried to write to invalid ipr %d\n", idx);
538 }
539
540 // no error...
541}
542
543void
544copyIprs(ThreadContext *src, ThreadContext *dest)
545{
546 for (int i = 0; i < NumInternalProcRegs; ++i)
547 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
548}
549
550} // namespace AlphaISA
551
552#if FULL_SYSTEM
553
554using namespace AlphaISA;
555
556Fault
557SimpleThread::hwrei()
558{
559 if (!(readPC() & 0x3))
560 return new UnimplementedOpcodeFault;
561
562 setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
563
564 CPA::cpa()->swAutoBegin(tc, readNextPC());
565
566 if (!misspeculating()) {
567 if (kernelStats)
568 kernelStats->hwrei();
569 }
570
571 // FIXME: XXX check for interrupts? XXX
572 return NoFault;
573}
574
575/**
576 * Check for special simulator handling of specific PAL calls.
577 * If return value is false, actual PAL call will be suppressed.
578 */
579bool
580SimpleThread::simPalCheck(int palFunc)
581{
582 if (kernelStats)
583 kernelStats->callpal(palFunc, tc);
584
585 switch (palFunc) {
586 case PAL::halt:
587 halt();
588 if (--System::numSystemsRunning == 0)
589 exitSimLoop("all cpus halted");
590 break;
591
592 case PAL::bpt:
593 case PAL::bugchk:
594 if (system->breakpoint())
595 return false;
596 break;
597 }
598
599 return true;
600}
601
602#endif // FULL_SYSTEM
|