1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#include "arch/alpha/faults.hh"
33#include "arch/alpha/isa_traits.hh"
34#include "arch/alpha/kernel_stats.hh"
35#include "arch/alpha/osfpal.hh"
36#include "arch/alpha/tlb.hh"
37#include "arch/alpha/kgdb.h"
38#include "base/remote_gdb.hh"
39#include "base/stats/events.hh"
40#include "config/full_system.hh"
41#include "cpu/base.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"
44#include "sim/debug.hh"
45#include "sim/sim_exit.hh"
46
47#if FULL_SYSTEM
48
49using namespace EV5;
50
51////////////////////////////////////////////////////////////////////////
52//
53// Machine dependent functions
54//
55void
56AlphaISA::initCPU(ThreadContext *tc, int cpuId)
57{
58 initIPRs(tc, cpuId);
59
60 tc->setIntReg(16, cpuId);
61 tc->setIntReg(0, cpuId);
62
63 AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
64
65 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
66 tc->setNextPC(tc->readPC() + sizeof(MachInst));
67
68 delete reset;
69}
70
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#include "arch/alpha/faults.hh"
33#include "arch/alpha/isa_traits.hh"
34#include "arch/alpha/kernel_stats.hh"
35#include "arch/alpha/osfpal.hh"
36#include "arch/alpha/tlb.hh"
37#include "arch/alpha/kgdb.h"
38#include "base/remote_gdb.hh"
39#include "base/stats/events.hh"
40#include "config/full_system.hh"
41#include "cpu/base.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"
44#include "sim/debug.hh"
45#include "sim/sim_exit.hh"
46
47#if FULL_SYSTEM
48
49using namespace EV5;
50
51////////////////////////////////////////////////////////////////////////
52//
53// Machine dependent functions
54//
55void
56AlphaISA::initCPU(ThreadContext *tc, int cpuId)
57{
58 initIPRs(tc, cpuId);
59
60 tc->setIntReg(16, cpuId);
61 tc->setIntReg(0, cpuId);
62
63 AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
64
65 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
66 tc->setNextPC(tc->readPC() + sizeof(MachInst));
67
68 delete reset;
69}
70
|
71////////////////////////////////////////////////////////////////////////
72//
73//
74//
75void
76AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
77{
78 for (int i = 0; i < NumInternalProcRegs; ++i) {
79 tc->setMiscRegNoEffect(i, 0);
80 }
| |
81
| 71
|
82 tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
83 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
84 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
85}
86
87
| |
88template <class CPU>
89void
90AlphaISA::processInterrupts(CPU *cpu)
91{
92 //Check if there are any outstanding interrupts
93 //Handle the interrupts
94 int ipl = 0;
95 int summary = 0;
96
97 if (cpu->readMiscRegNoEffect(IPR_ASTRR))
98 panic("asynchronous traps not implemented\n");
99
100 if (cpu->readMiscRegNoEffect(IPR_SIRR)) {
101 for (int i = INTLEVEL_SOFTWARE_MIN;
102 i < INTLEVEL_SOFTWARE_MAX; i++) {
103 if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
104 // See table 4-19 of the 21164 hardware reference
105 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
106 summary |= (ULL(1) << i);
107 }
108 }
109 }
110
111 uint64_t interrupts = cpu->intr_status();
112
113 if (interrupts) {
114 for (int i = INTLEVEL_EXTERNAL_MIN;
115 i < INTLEVEL_EXTERNAL_MAX; i++) {
116 if (interrupts & (ULL(1) << i)) {
117 // See table 4-19 of the 21164 hardware reference
118 ipl = i;
119 summary |= (ULL(1) << i);
120 }
121 }
122 }
123
124 if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) {
125 cpu->setMiscRegNoEffect(IPR_ISR, summary);
126 cpu->setMiscRegNoEffect(IPR_INTID, ipl);
127 cpu->trap(new InterruptFault);
128 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
129 cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
130 }
131
132}
133
134template <class CPU>
135void
136AlphaISA::zeroRegisters(CPU *cpu)
137{
138 // Insure ISA semantics
139 // (no longer very clean due to the change in setIntReg() in the
140 // cpu model. Consider changing later.)
141 cpu->thread->setIntReg(ZeroReg, 0);
142 cpu->thread->setFloatReg(ZeroReg, 0.0);
143}
144
145Fault
146SimpleThread::hwrei()
147{
148 if (!(readPC() & 0x3))
149 return new UnimplementedOpcodeFault;
150
151 setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
152
153 if (!misspeculating()) {
154 if (kernelStats)
155 kernelStats->hwrei();
156 }
157
158 // FIXME: XXX check for interrupts? XXX
159 return NoFault;
160}
161
162int
163AlphaISA::MiscRegFile::getInstAsid()
164{
165 return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
166}
167
168int
169AlphaISA::MiscRegFile::getDataAsid()
170{
171 return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
172}
173
| 72template <class CPU>
73void
74AlphaISA::processInterrupts(CPU *cpu)
75{
76 //Check if there are any outstanding interrupts
77 //Handle the interrupts
78 int ipl = 0;
79 int summary = 0;
80
81 if (cpu->readMiscRegNoEffect(IPR_ASTRR))
82 panic("asynchronous traps not implemented\n");
83
84 if (cpu->readMiscRegNoEffect(IPR_SIRR)) {
85 for (int i = INTLEVEL_SOFTWARE_MIN;
86 i < INTLEVEL_SOFTWARE_MAX; i++) {
87 if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
88 // See table 4-19 of the 21164 hardware reference
89 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
90 summary |= (ULL(1) << i);
91 }
92 }
93 }
94
95 uint64_t interrupts = cpu->intr_status();
96
97 if (interrupts) {
98 for (int i = INTLEVEL_EXTERNAL_MIN;
99 i < INTLEVEL_EXTERNAL_MAX; i++) {
100 if (interrupts & (ULL(1) << i)) {
101 // See table 4-19 of the 21164 hardware reference
102 ipl = i;
103 summary |= (ULL(1) << i);
104 }
105 }
106 }
107
108 if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) {
109 cpu->setMiscRegNoEffect(IPR_ISR, summary);
110 cpu->setMiscRegNoEffect(IPR_INTID, ipl);
111 cpu->trap(new InterruptFault);
112 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
113 cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
114 }
115
116}
117
118template <class CPU>
119void
120AlphaISA::zeroRegisters(CPU *cpu)
121{
122 // Insure ISA semantics
123 // (no longer very clean due to the change in setIntReg() in the
124 // cpu model. Consider changing later.)
125 cpu->thread->setIntReg(ZeroReg, 0);
126 cpu->thread->setFloatReg(ZeroReg, 0.0);
127}
128
129Fault
130SimpleThread::hwrei()
131{
132 if (!(readPC() & 0x3))
133 return new UnimplementedOpcodeFault;
134
135 setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
136
137 if (!misspeculating()) {
138 if (kernelStats)
139 kernelStats->hwrei();
140 }
141
142 // FIXME: XXX check for interrupts? XXX
143 return NoFault;
144}
145
146int
147AlphaISA::MiscRegFile::getInstAsid()
148{
149 return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
150}
151
152int
153AlphaISA::MiscRegFile::getDataAsid()
154{
155 return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
156}
157
|
| 158#endif
159
160////////////////////////////////////////////////////////////////////////
161//
162//
163//
164void
165AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
166{
167 for (int i = 0; i < NumInternalProcRegs; ++i) {
168 tc->setMiscRegNoEffect(i, 0);
169 }
170
171 tc->setMiscRegNoEffect(IPR_PAL_BASE, EV5::PalBase);
172 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
173 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
174}
175
|
174AlphaISA::MiscReg
175AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
176{
177 uint64_t retval = 0; // return value, default 0
178
179 switch (idx) {
180 case AlphaISA::IPR_PALtemp0:
181 case AlphaISA::IPR_PALtemp1:
182 case AlphaISA::IPR_PALtemp2:
183 case AlphaISA::IPR_PALtemp3:
184 case AlphaISA::IPR_PALtemp4:
185 case AlphaISA::IPR_PALtemp5:
186 case AlphaISA::IPR_PALtemp6:
187 case AlphaISA::IPR_PALtemp7:
188 case AlphaISA::IPR_PALtemp8:
189 case AlphaISA::IPR_PALtemp9:
190 case AlphaISA::IPR_PALtemp10:
191 case AlphaISA::IPR_PALtemp11:
192 case AlphaISA::IPR_PALtemp12:
193 case AlphaISA::IPR_PALtemp13:
194 case AlphaISA::IPR_PALtemp14:
195 case AlphaISA::IPR_PALtemp15:
196 case AlphaISA::IPR_PALtemp16:
197 case AlphaISA::IPR_PALtemp17:
198 case AlphaISA::IPR_PALtemp18:
199 case AlphaISA::IPR_PALtemp19:
200 case AlphaISA::IPR_PALtemp20:
201 case AlphaISA::IPR_PALtemp21:
202 case AlphaISA::IPR_PALtemp22:
203 case AlphaISA::IPR_PALtemp23:
204 case AlphaISA::IPR_PAL_BASE:
205
206 case AlphaISA::IPR_IVPTBR:
207 case AlphaISA::IPR_DC_MODE:
208 case AlphaISA::IPR_MAF_MODE:
209 case AlphaISA::IPR_ISR:
210 case AlphaISA::IPR_EXC_ADDR:
211 case AlphaISA::IPR_IC_PERR_STAT:
212 case AlphaISA::IPR_DC_PERR_STAT:
213 case AlphaISA::IPR_MCSR:
214 case AlphaISA::IPR_ASTRR:
215 case AlphaISA::IPR_ASTER:
216 case AlphaISA::IPR_SIRR:
217 case AlphaISA::IPR_ICSR:
218 case AlphaISA::IPR_ICM:
219 case AlphaISA::IPR_DTB_CM:
220 case AlphaISA::IPR_IPLR:
221 case AlphaISA::IPR_INTID:
222 case AlphaISA::IPR_PMCTR:
223 // no side-effect
224 retval = ipr[idx];
225 break;
226
227 case AlphaISA::IPR_CC:
228 retval |= ipr[idx] & ULL(0xffffffff00000000);
229 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
230 break;
231
232 case AlphaISA::IPR_VA:
233 retval = ipr[idx];
234 break;
235
236 case AlphaISA::IPR_VA_FORM:
237 case AlphaISA::IPR_MM_STAT:
238 case AlphaISA::IPR_IFAULT_VA_FORM:
239 case AlphaISA::IPR_EXC_MASK:
240 case AlphaISA::IPR_EXC_SUM:
241 retval = ipr[idx];
242 break;
243
244 case AlphaISA::IPR_DTB_PTE:
245 {
246 AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
247
248 retval |= ((uint64_t)pte.ppn & ULL(0x7ffffff)) << 32;
249 retval |= ((uint64_t)pte.xre & ULL(0xf)) << 8;
250 retval |= ((uint64_t)pte.xwe & ULL(0xf)) << 12;
251 retval |= ((uint64_t)pte.fonr & ULL(0x1)) << 1;
252 retval |= ((uint64_t)pte.fonw & ULL(0x1))<< 2;
253 retval |= ((uint64_t)pte.asma & ULL(0x1)) << 4;
254 retval |= ((uint64_t)pte.asn & ULL(0x7f)) << 57;
255 }
256 break;
257
258 // write only registers
259 case AlphaISA::IPR_HWINT_CLR:
260 case AlphaISA::IPR_SL_XMIT:
261 case AlphaISA::IPR_DC_FLUSH:
262 case AlphaISA::IPR_IC_FLUSH:
263 case AlphaISA::IPR_ALT_MODE:
264 case AlphaISA::IPR_DTB_IA:
265 case AlphaISA::IPR_DTB_IAP:
266 case AlphaISA::IPR_ITB_IA:
267 case AlphaISA::IPR_ITB_IAP:
268 panic("Tried to read write only register %d\n", idx);
269 break;
270
271 default:
272 // invalid IPR
273 panic("Tried to read from invalid ipr %d\n", idx);
274 break;
275 }
276
277 return retval;
278}
279
280#ifdef DEBUG
281// Cause the simulator to break when changing to the following IPL
282int break_ipl = -1;
283#endif
284
285void
286AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
287{
288 uint64_t old;
289
290 if (tc->misspeculating())
291 return;
292
293 switch (idx) {
294 case AlphaISA::IPR_PALtemp0:
295 case AlphaISA::IPR_PALtemp1:
296 case AlphaISA::IPR_PALtemp2:
297 case AlphaISA::IPR_PALtemp3:
298 case AlphaISA::IPR_PALtemp4:
299 case AlphaISA::IPR_PALtemp5:
300 case AlphaISA::IPR_PALtemp6:
301 case AlphaISA::IPR_PALtemp7:
302 case AlphaISA::IPR_PALtemp8:
303 case AlphaISA::IPR_PALtemp9:
304 case AlphaISA::IPR_PALtemp10:
305 case AlphaISA::IPR_PALtemp11:
306 case AlphaISA::IPR_PALtemp12:
307 case AlphaISA::IPR_PALtemp13:
308 case AlphaISA::IPR_PALtemp14:
309 case AlphaISA::IPR_PALtemp15:
310 case AlphaISA::IPR_PALtemp16:
311 case AlphaISA::IPR_PALtemp17:
312 case AlphaISA::IPR_PALtemp18:
313 case AlphaISA::IPR_PALtemp19:
314 case AlphaISA::IPR_PALtemp20:
315 case AlphaISA::IPR_PALtemp21:
316 case AlphaISA::IPR_PALtemp22:
317 case AlphaISA::IPR_PAL_BASE:
318 case AlphaISA::IPR_IC_PERR_STAT:
319 case AlphaISA::IPR_DC_PERR_STAT:
320 case AlphaISA::IPR_PMCTR:
321 // write entire quad w/ no side-effect
322 ipr[idx] = val;
323 break;
324
325 case AlphaISA::IPR_CC_CTL:
326 // This IPR resets the cycle counter. We assume this only
327 // happens once... let's verify that.
328 assert(ipr[idx] == 0);
329 ipr[idx] = 1;
330 break;
331
332 case AlphaISA::IPR_CC:
333 // This IPR only writes the upper 64 bits. It's ok to write
334 // all 64 here since we mask out the lower 32 in rpcc (see
335 // isa_desc).
336 ipr[idx] = val;
337 break;
338
339 case AlphaISA::IPR_PALtemp23:
340 // write entire quad w/ no side-effect
341 old = ipr[idx];
342 ipr[idx] = val;
| 176AlphaISA::MiscReg
177AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
178{
179 uint64_t retval = 0; // return value, default 0
180
181 switch (idx) {
182 case AlphaISA::IPR_PALtemp0:
183 case AlphaISA::IPR_PALtemp1:
184 case AlphaISA::IPR_PALtemp2:
185 case AlphaISA::IPR_PALtemp3:
186 case AlphaISA::IPR_PALtemp4:
187 case AlphaISA::IPR_PALtemp5:
188 case AlphaISA::IPR_PALtemp6:
189 case AlphaISA::IPR_PALtemp7:
190 case AlphaISA::IPR_PALtemp8:
191 case AlphaISA::IPR_PALtemp9:
192 case AlphaISA::IPR_PALtemp10:
193 case AlphaISA::IPR_PALtemp11:
194 case AlphaISA::IPR_PALtemp12:
195 case AlphaISA::IPR_PALtemp13:
196 case AlphaISA::IPR_PALtemp14:
197 case AlphaISA::IPR_PALtemp15:
198 case AlphaISA::IPR_PALtemp16:
199 case AlphaISA::IPR_PALtemp17:
200 case AlphaISA::IPR_PALtemp18:
201 case AlphaISA::IPR_PALtemp19:
202 case AlphaISA::IPR_PALtemp20:
203 case AlphaISA::IPR_PALtemp21:
204 case AlphaISA::IPR_PALtemp22:
205 case AlphaISA::IPR_PALtemp23:
206 case AlphaISA::IPR_PAL_BASE:
207
208 case AlphaISA::IPR_IVPTBR:
209 case AlphaISA::IPR_DC_MODE:
210 case AlphaISA::IPR_MAF_MODE:
211 case AlphaISA::IPR_ISR:
212 case AlphaISA::IPR_EXC_ADDR:
213 case AlphaISA::IPR_IC_PERR_STAT:
214 case AlphaISA::IPR_DC_PERR_STAT:
215 case AlphaISA::IPR_MCSR:
216 case AlphaISA::IPR_ASTRR:
217 case AlphaISA::IPR_ASTER:
218 case AlphaISA::IPR_SIRR:
219 case AlphaISA::IPR_ICSR:
220 case AlphaISA::IPR_ICM:
221 case AlphaISA::IPR_DTB_CM:
222 case AlphaISA::IPR_IPLR:
223 case AlphaISA::IPR_INTID:
224 case AlphaISA::IPR_PMCTR:
225 // no side-effect
226 retval = ipr[idx];
227 break;
228
229 case AlphaISA::IPR_CC:
230 retval |= ipr[idx] & ULL(0xffffffff00000000);
231 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
232 break;
233
234 case AlphaISA::IPR_VA:
235 retval = ipr[idx];
236 break;
237
238 case AlphaISA::IPR_VA_FORM:
239 case AlphaISA::IPR_MM_STAT:
240 case AlphaISA::IPR_IFAULT_VA_FORM:
241 case AlphaISA::IPR_EXC_MASK:
242 case AlphaISA::IPR_EXC_SUM:
243 retval = ipr[idx];
244 break;
245
246 case AlphaISA::IPR_DTB_PTE:
247 {
248 AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
249
250 retval |= ((uint64_t)pte.ppn & ULL(0x7ffffff)) << 32;
251 retval |= ((uint64_t)pte.xre & ULL(0xf)) << 8;
252 retval |= ((uint64_t)pte.xwe & ULL(0xf)) << 12;
253 retval |= ((uint64_t)pte.fonr & ULL(0x1)) << 1;
254 retval |= ((uint64_t)pte.fonw & ULL(0x1))<< 2;
255 retval |= ((uint64_t)pte.asma & ULL(0x1)) << 4;
256 retval |= ((uint64_t)pte.asn & ULL(0x7f)) << 57;
257 }
258 break;
259
260 // write only registers
261 case AlphaISA::IPR_HWINT_CLR:
262 case AlphaISA::IPR_SL_XMIT:
263 case AlphaISA::IPR_DC_FLUSH:
264 case AlphaISA::IPR_IC_FLUSH:
265 case AlphaISA::IPR_ALT_MODE:
266 case AlphaISA::IPR_DTB_IA:
267 case AlphaISA::IPR_DTB_IAP:
268 case AlphaISA::IPR_ITB_IA:
269 case AlphaISA::IPR_ITB_IAP:
270 panic("Tried to read write only register %d\n", idx);
271 break;
272
273 default:
274 // invalid IPR
275 panic("Tried to read from invalid ipr %d\n", idx);
276 break;
277 }
278
279 return retval;
280}
281
282#ifdef DEBUG
283// Cause the simulator to break when changing to the following IPL
284int break_ipl = -1;
285#endif
286
287void
288AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
289{
290 uint64_t old;
291
292 if (tc->misspeculating())
293 return;
294
295 switch (idx) {
296 case AlphaISA::IPR_PALtemp0:
297 case AlphaISA::IPR_PALtemp1:
298 case AlphaISA::IPR_PALtemp2:
299 case AlphaISA::IPR_PALtemp3:
300 case AlphaISA::IPR_PALtemp4:
301 case AlphaISA::IPR_PALtemp5:
302 case AlphaISA::IPR_PALtemp6:
303 case AlphaISA::IPR_PALtemp7:
304 case AlphaISA::IPR_PALtemp8:
305 case AlphaISA::IPR_PALtemp9:
306 case AlphaISA::IPR_PALtemp10:
307 case AlphaISA::IPR_PALtemp11:
308 case AlphaISA::IPR_PALtemp12:
309 case AlphaISA::IPR_PALtemp13:
310 case AlphaISA::IPR_PALtemp14:
311 case AlphaISA::IPR_PALtemp15:
312 case AlphaISA::IPR_PALtemp16:
313 case AlphaISA::IPR_PALtemp17:
314 case AlphaISA::IPR_PALtemp18:
315 case AlphaISA::IPR_PALtemp19:
316 case AlphaISA::IPR_PALtemp20:
317 case AlphaISA::IPR_PALtemp21:
318 case AlphaISA::IPR_PALtemp22:
319 case AlphaISA::IPR_PAL_BASE:
320 case AlphaISA::IPR_IC_PERR_STAT:
321 case AlphaISA::IPR_DC_PERR_STAT:
322 case AlphaISA::IPR_PMCTR:
323 // write entire quad w/ no side-effect
324 ipr[idx] = val;
325 break;
326
327 case AlphaISA::IPR_CC_CTL:
328 // This IPR resets the cycle counter. We assume this only
329 // happens once... let's verify that.
330 assert(ipr[idx] == 0);
331 ipr[idx] = 1;
332 break;
333
334 case AlphaISA::IPR_CC:
335 // This IPR only writes the upper 64 bits. It's ok to write
336 // all 64 here since we mask out the lower 32 in rpcc (see
337 // isa_desc).
338 ipr[idx] = val;
339 break;
340
341 case AlphaISA::IPR_PALtemp23:
342 // write entire quad w/ no side-effect
343 old = ipr[idx];
344 ipr[idx] = val;
|
| 345#if FULL_SYSTEM
|
343 if (tc->getKernelStats())
344 tc->getKernelStats()->context(old, val, tc);
| 346 if (tc->getKernelStats())
347 tc->getKernelStats()->context(old, val, tc);
|
| 348#endif
|
345 break;
346
347 case AlphaISA::IPR_DTB_PTE:
348 // write entire quad w/ no side-effect, tag is forthcoming
349 ipr[idx] = val;
350 break;
351
352 case AlphaISA::IPR_EXC_ADDR:
353 // second least significant bit in PC is always zero
354 ipr[idx] = val & ~2;
355 break;
356
357 case AlphaISA::IPR_ASTRR:
358 case AlphaISA::IPR_ASTER:
359 // only write least significant four bits - privilege mask
360 ipr[idx] = val & 0xf;
361 break;
362
363 case AlphaISA::IPR_IPLR:
364#ifdef DEBUG
365 if (break_ipl != -1 && break_ipl == (val & 0x1f))
366 debug_break();
367#endif
368
369 // only write least significant five bits - interrupt level
370 ipr[idx] = val & 0x1f;
| 349 break;
350
351 case AlphaISA::IPR_DTB_PTE:
352 // write entire quad w/ no side-effect, tag is forthcoming
353 ipr[idx] = val;
354 break;
355
356 case AlphaISA::IPR_EXC_ADDR:
357 // second least significant bit in PC is always zero
358 ipr[idx] = val & ~2;
359 break;
360
361 case AlphaISA::IPR_ASTRR:
362 case AlphaISA::IPR_ASTER:
363 // only write least significant four bits - privilege mask
364 ipr[idx] = val & 0xf;
365 break;
366
367 case AlphaISA::IPR_IPLR:
368#ifdef DEBUG
369 if (break_ipl != -1 && break_ipl == (val & 0x1f))
370 debug_break();
371#endif
372
373 // only write least significant five bits - interrupt level
374 ipr[idx] = val & 0x1f;
|
| 375#if FULL_SYSTEM
|
371 if (tc->getKernelStats())
372 tc->getKernelStats()->swpipl(ipr[idx]);
| 376 if (tc->getKernelStats())
377 tc->getKernelStats()->swpipl(ipr[idx]);
|
| 378#endif
|
373 break;
374
375 case AlphaISA::IPR_DTB_CM:
| 379 break;
380
381 case AlphaISA::IPR_DTB_CM:
|
| 382#if FULL_SYSTEM
|
376 if (val & 0x18) {
377 if (tc->getKernelStats())
378 tc->getKernelStats()->mode(TheISA::Kernel::user, tc);
379 } else {
380 if (tc->getKernelStats())
381 tc->getKernelStats()->mode(TheISA::Kernel::kernel, tc);
382 }
| 383 if (val & 0x18) {
384 if (tc->getKernelStats())
385 tc->getKernelStats()->mode(TheISA::Kernel::user, tc);
386 } else {
387 if (tc->getKernelStats())
388 tc->getKernelStats()->mode(TheISA::Kernel::kernel, tc);
389 }
|
| 390#endif
|
383
384 case AlphaISA::IPR_ICM:
385 // only write two mode bits - processor mode
386 ipr[idx] = val & 0x18;
387 break;
388
389 case AlphaISA::IPR_ALT_MODE:
390 // only write two mode bits - processor mode
391 ipr[idx] = val & 0x18;
392 break;
393
394 case AlphaISA::IPR_MCSR:
395 // more here after optimization...
396 ipr[idx] = val;
397 break;
398
399 case AlphaISA::IPR_SIRR:
400 // only write software interrupt mask
401 ipr[idx] = val & 0x7fff0;
402 break;
403
404 case AlphaISA::IPR_ICSR:
405 ipr[idx] = val & ULL(0xffffff0300);
406 break;
407
408 case AlphaISA::IPR_IVPTBR:
409 case AlphaISA::IPR_MVPTBR:
410 ipr[idx] = val & ULL(0xffffffffc0000000);
411 break;
412
413 case AlphaISA::IPR_DC_TEST_CTL:
414 ipr[idx] = val & 0x1ffb;
415 break;
416
417 case AlphaISA::IPR_DC_MODE:
418 case AlphaISA::IPR_MAF_MODE:
419 ipr[idx] = val & 0x3f;
420 break;
421
422 case AlphaISA::IPR_ITB_ASN:
423 ipr[idx] = val & 0x7f0;
424 break;
425
426 case AlphaISA::IPR_DTB_ASN:
427 ipr[idx] = val & ULL(0xfe00000000000000);
428 break;
429
430 case AlphaISA::IPR_EXC_SUM:
431 case AlphaISA::IPR_EXC_MASK:
432 // any write to this register clears it
433 ipr[idx] = 0;
434 break;
435
436 case AlphaISA::IPR_INTID:
437 case AlphaISA::IPR_SL_RCV:
438 case AlphaISA::IPR_MM_STAT:
439 case AlphaISA::IPR_ITB_PTE_TEMP:
440 case AlphaISA::IPR_DTB_PTE_TEMP:
441 // read-only registers
442 panic("Tried to write read only ipr %d\n", idx);
443
444 case AlphaISA::IPR_HWINT_CLR:
445 case AlphaISA::IPR_SL_XMIT:
446 case AlphaISA::IPR_DC_FLUSH:
447 case AlphaISA::IPR_IC_FLUSH:
448 // the following are write only
449 ipr[idx] = val;
450 break;
451
452 case AlphaISA::IPR_DTB_IA:
453 // really a control write
454 ipr[idx] = 0;
455
456 tc->getDTBPtr()->flushAll();
457 break;
458
459 case AlphaISA::IPR_DTB_IAP:
460 // really a control write
461 ipr[idx] = 0;
462
463 tc->getDTBPtr()->flushProcesses();
464 break;
465
466 case AlphaISA::IPR_DTB_IS:
467 // really a control write
468 ipr[idx] = val;
469
470 tc->getDTBPtr()->flushAddr(val,
| 391
392 case AlphaISA::IPR_ICM:
393 // only write two mode bits - processor mode
394 ipr[idx] = val & 0x18;
395 break;
396
397 case AlphaISA::IPR_ALT_MODE:
398 // only write two mode bits - processor mode
399 ipr[idx] = val & 0x18;
400 break;
401
402 case AlphaISA::IPR_MCSR:
403 // more here after optimization...
404 ipr[idx] = val;
405 break;
406
407 case AlphaISA::IPR_SIRR:
408 // only write software interrupt mask
409 ipr[idx] = val & 0x7fff0;
410 break;
411
412 case AlphaISA::IPR_ICSR:
413 ipr[idx] = val & ULL(0xffffff0300);
414 break;
415
416 case AlphaISA::IPR_IVPTBR:
417 case AlphaISA::IPR_MVPTBR:
418 ipr[idx] = val & ULL(0xffffffffc0000000);
419 break;
420
421 case AlphaISA::IPR_DC_TEST_CTL:
422 ipr[idx] = val & 0x1ffb;
423 break;
424
425 case AlphaISA::IPR_DC_MODE:
426 case AlphaISA::IPR_MAF_MODE:
427 ipr[idx] = val & 0x3f;
428 break;
429
430 case AlphaISA::IPR_ITB_ASN:
431 ipr[idx] = val & 0x7f0;
432 break;
433
434 case AlphaISA::IPR_DTB_ASN:
435 ipr[idx] = val & ULL(0xfe00000000000000);
436 break;
437
438 case AlphaISA::IPR_EXC_SUM:
439 case AlphaISA::IPR_EXC_MASK:
440 // any write to this register clears it
441 ipr[idx] = 0;
442 break;
443
444 case AlphaISA::IPR_INTID:
445 case AlphaISA::IPR_SL_RCV:
446 case AlphaISA::IPR_MM_STAT:
447 case AlphaISA::IPR_ITB_PTE_TEMP:
448 case AlphaISA::IPR_DTB_PTE_TEMP:
449 // read-only registers
450 panic("Tried to write read only ipr %d\n", idx);
451
452 case AlphaISA::IPR_HWINT_CLR:
453 case AlphaISA::IPR_SL_XMIT:
454 case AlphaISA::IPR_DC_FLUSH:
455 case AlphaISA::IPR_IC_FLUSH:
456 // the following are write only
457 ipr[idx] = val;
458 break;
459
460 case AlphaISA::IPR_DTB_IA:
461 // really a control write
462 ipr[idx] = 0;
463
464 tc->getDTBPtr()->flushAll();
465 break;
466
467 case AlphaISA::IPR_DTB_IAP:
468 // really a control write
469 ipr[idx] = 0;
470
471 tc->getDTBPtr()->flushProcesses();
472 break;
473
474 case AlphaISA::IPR_DTB_IS:
475 // really a control write
476 ipr[idx] = val;
477
478 tc->getDTBPtr()->flushAddr(val,
|
471 DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
| 479 EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
|
472 break;
473
474 case AlphaISA::IPR_DTB_TAG: {
475 struct AlphaISA::PTE pte;
476
477 // FIXME: granularity hints NYI...
| 480 break;
481
482 case AlphaISA::IPR_DTB_TAG: {
483 struct AlphaISA::PTE pte;
484
485 // FIXME: granularity hints NYI...
|
478 if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
| 486 if (EV5::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
|
479 panic("PTE GH field != 0");
480
481 // write entire quad
482 ipr[idx] = val;
483
484 // construct PTE for new entry
| 487 panic("PTE GH field != 0");
488
489 // write entire quad
490 ipr[idx] = val;
491
492 // construct PTE for new entry
|
485 pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
486 pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
487 pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
488 pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
489 pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
490 pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
491 pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
| 493 pte.ppn = EV5::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
494 pte.xre = EV5::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
495 pte.xwe = EV5::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
496 pte.fonr = EV5::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
497 pte.fonw = EV5::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
498 pte.asma = EV5::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
499 pte.asn = EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
|
492
493 // insert new TAG/PTE value into data TLB
494 tc->getDTBPtr()->insert(val, pte);
495 }
496 break;
497
498 case AlphaISA::IPR_ITB_PTE: {
499 struct AlphaISA::PTE pte;
500
501 // FIXME: granularity hints NYI...
| 500
501 // insert new TAG/PTE value into data TLB
502 tc->getDTBPtr()->insert(val, pte);
503 }
504 break;
505
506 case AlphaISA::IPR_ITB_PTE: {
507 struct AlphaISA::PTE pte;
508
509 // FIXME: granularity hints NYI...
|
502 if (ITB_PTE_GH(val) != 0)
| 510 if (EV5::ITB_PTE_GH(val) != 0)
|
503 panic("PTE GH field != 0");
504
505 // write entire quad
506 ipr[idx] = val;
507
508 // construct PTE for new entry
| 511 panic("PTE GH field != 0");
512
513 // write entire quad
514 ipr[idx] = val;
515
516 // construct PTE for new entry
|
509 pte.ppn = ITB_PTE_PPN(val);
510 pte.xre = ITB_PTE_XRE(val);
| 517 pte.ppn = EV5::ITB_PTE_PPN(val);
518 pte.xre = EV5::ITB_PTE_XRE(val);
|
511 pte.xwe = 0;
| 519 pte.xwe = 0;
|
512 pte.fonr = ITB_PTE_FONR(val);
513 pte.fonw = ITB_PTE_FONW(val);
514 pte.asma = ITB_PTE_ASMA(val);
515 pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
| 520 pte.fonr = EV5::ITB_PTE_FONR(val);
521 pte.fonw = EV5::ITB_PTE_FONW(val);
522 pte.asma = EV5::ITB_PTE_ASMA(val);
523 pte.asn = EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
|
516
517 // insert new TAG/PTE value into data TLB
518 tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
519 }
520 break;
521
522 case AlphaISA::IPR_ITB_IA:
523 // really a control write
524 ipr[idx] = 0;
525
526 tc->getITBPtr()->flushAll();
527 break;
528
529 case AlphaISA::IPR_ITB_IAP:
530 // really a control write
531 ipr[idx] = 0;
532
533 tc->getITBPtr()->flushProcesses();
534 break;
535
536 case AlphaISA::IPR_ITB_IS:
537 // really a control write
538 ipr[idx] = val;
539
540 tc->getITBPtr()->flushAddr(val,
| 524
525 // insert new TAG/PTE value into data TLB
526 tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
527 }
528 break;
529
530 case AlphaISA::IPR_ITB_IA:
531 // really a control write
532 ipr[idx] = 0;
533
534 tc->getITBPtr()->flushAll();
535 break;
536
537 case AlphaISA::IPR_ITB_IAP:
538 // really a control write
539 ipr[idx] = 0;
540
541 tc->getITBPtr()->flushProcesses();
542 break;
543
544 case AlphaISA::IPR_ITB_IS:
545 // really a control write
546 ipr[idx] = val;
547
548 tc->getITBPtr()->flushAddr(val,
|
541 ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
| 549 EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
|
542 break;
543
544 default:
545 // invalid IPR
546 panic("Tried to write to invalid ipr %d\n", idx);
547 }
548
549 // no error...
550}
551
552
553void
554AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
555{
556 for (int i = 0; i < NumInternalProcRegs; ++i) {
557 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
558 }
559}
560
| 550 break;
551
552 default:
553 // invalid IPR
554 panic("Tried to write to invalid ipr %d\n", idx);
555 }
556
557 // no error...
558}
559
560
561void
562AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
563{
564 for (int i = 0; i < NumInternalProcRegs; ++i) {
565 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
566 }
567}
568
|
| 569#if FULL_SYSTEM
|
561
562/**
563 * Check for special simulator handling of specific PAL calls.
564 * If return value is false, actual PAL call will be suppressed.
565 */
566bool
567SimpleThread::simPalCheck(int palFunc)
568{
569 if (kernelStats)
570 kernelStats->callpal(palFunc, tc);
571
572 switch (palFunc) {
573 case PAL::halt:
574 halt();
575 if (--System::numSystemsRunning == 0)
576 exitSimLoop("all cpus halted");
577 break;
578
579 case PAL::bpt:
580 case PAL::bugchk:
581 if (system->breakpoint())
582 return false;
583 break;
584 }
585
586 return true;
587}
588
589#endif // FULL_SYSTEM
| 570
571/**
572 * Check for special simulator handling of specific PAL calls.
573 * If return value is false, actual PAL call will be suppressed.
574 */
575bool
576SimpleThread::simPalCheck(int palFunc)
577{
578 if (kernelStats)
579 kernelStats->callpal(palFunc, tc);
580
581 switch (palFunc) {
582 case PAL::halt:
583 halt();
584 if (--System::numSystemsRunning == 0)
585 exitSimLoop("all cpus halted");
586 break;
587
588 case PAL::bpt:
589 case PAL::bugchk:
590 if (system->breakpoint())
591 return false;
592 break;
593 }
594
595 return true;
596}
597
598#endif // FULL_SYSTEM
|