1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
| 27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
|
27 */
28
29#include "arch/alpha/tlb.hh"
30#include "arch/alpha/isa_traits.hh"
31#include "arch/alpha/osfpal.hh"
32#include "base/kgdb.h"
33#include "base/remote_gdb.hh"
34#include "base/stats/events.hh"
35#include "config/full_system.hh"
36#include "cpu/base.hh"
37#include "cpu/cpu_exec_context.hh"
38#include "cpu/exec_context.hh"
39#include "kern/kernel_stats.hh"
40#include "sim/debug.hh"
41#include "sim/sim_events.hh"
42
43#if FULL_SYSTEM
44
45using namespace EV5;
46
47////////////////////////////////////////////////////////////////////////
48//
49// Machine dependent functions
50//
51void
52AlphaISA::initCPU(ExecContext *xc, int cpuId)
53{
54 initIPRs(xc, cpuId);
55
56 xc->setIntReg(16, cpuId);
57 xc->setIntReg(0, cpuId);
58
59 xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect());
60 xc->setNextPC(xc->readPC() + sizeof(MachInst));
61}
62
63////////////////////////////////////////////////////////////////////////
64//
65//
66//
67void
68AlphaISA::initIPRs(ExecContext *xc, int cpuId)
69{
70 for (int i = 0; i < NumInternalProcRegs; ++i) {
71 xc->setMiscReg(i, 0);
72 }
73
74 xc->setMiscReg(IPR_PAL_BASE, PalBase);
75 xc->setMiscReg(IPR_MCSR, 0x6);
76 xc->setMiscReg(IPR_PALtemp16, cpuId);
77}
78
79
80template <class CPU>
81void
82AlphaISA::processInterrupts(CPU *cpu)
83{
84 //Check if there are any outstanding interrupts
85 //Handle the interrupts
86 int ipl = 0;
87 int summary = 0;
88
89 cpu->checkInterrupts = false;
90
91 if (cpu->readMiscReg(IPR_ASTRR))
92 panic("asynchronous traps not implemented\n");
93
94 if (cpu->readMiscReg(IPR_SIRR)) {
95 for (int i = INTLEVEL_SOFTWARE_MIN;
96 i < INTLEVEL_SOFTWARE_MAX; i++) {
97 if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
98 // See table 4-19 of the 21164 hardware reference
99 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
100 summary |= (ULL(1) << i);
101 }
102 }
103 }
104
105 uint64_t interrupts = cpu->intr_status();
106
107 if (interrupts) {
108 for (int i = INTLEVEL_EXTERNAL_MIN;
109 i < INTLEVEL_EXTERNAL_MAX; i++) {
110 if (interrupts & (ULL(1) << i)) {
111 // See table 4-19 of the 21164 hardware reference
112 ipl = i;
113 summary |= (ULL(1) << i);
114 }
115 }
116 }
117
118 if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
119 cpu->setMiscReg(IPR_ISR, summary);
120 cpu->setMiscReg(IPR_INTID, ipl);
121 cpu->trap(new InterruptFault);
122 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
123 cpu->readMiscReg(IPR_IPLR), ipl, summary);
124 }
125
126}
127
128template <class CPU>
129void
130AlphaISA::zeroRegisters(CPU *cpu)
131{
132 // Insure ISA semantics
133 // (no longer very clean due to the change in setIntReg() in the
134 // cpu model. Consider changing later.)
135 cpu->cpuXC->setIntReg(ZeroReg, 0);
136 cpu->cpuXC->setFloatReg(ZeroReg, 0.0);
137}
138
139Fault
140CPUExecContext::hwrei()
141{
142 if (!inPalMode())
143 return new UnimplementedOpcodeFault;
144
145 setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
146
147 if (!misspeculating()) {
| 30 */
31
32#include "arch/alpha/tlb.hh"
33#include "arch/alpha/isa_traits.hh"
34#include "arch/alpha/osfpal.hh"
35#include "base/kgdb.h"
36#include "base/remote_gdb.hh"
37#include "base/stats/events.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/cpu_exec_context.hh"
41#include "cpu/exec_context.hh"
42#include "kern/kernel_stats.hh"
43#include "sim/debug.hh"
44#include "sim/sim_events.hh"
45
46#if FULL_SYSTEM
47
48using namespace EV5;
49
50////////////////////////////////////////////////////////////////////////
51//
52// Machine dependent functions
53//
54void
55AlphaISA::initCPU(ExecContext *xc, int cpuId)
56{
57 initIPRs(xc, cpuId);
58
59 xc->setIntReg(16, cpuId);
60 xc->setIntReg(0, cpuId);
61
62 xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect());
63 xc->setNextPC(xc->readPC() + sizeof(MachInst));
64}
65
66////////////////////////////////////////////////////////////////////////
67//
68//
69//
70void
71AlphaISA::initIPRs(ExecContext *xc, int cpuId)
72{
73 for (int i = 0; i < NumInternalProcRegs; ++i) {
74 xc->setMiscReg(i, 0);
75 }
76
77 xc->setMiscReg(IPR_PAL_BASE, PalBase);
78 xc->setMiscReg(IPR_MCSR, 0x6);
79 xc->setMiscReg(IPR_PALtemp16, cpuId);
80}
81
82
83template <class CPU>
84void
85AlphaISA::processInterrupts(CPU *cpu)
86{
87 //Check if there are any outstanding interrupts
88 //Handle the interrupts
89 int ipl = 0;
90 int summary = 0;
91
92 cpu->checkInterrupts = false;
93
94 if (cpu->readMiscReg(IPR_ASTRR))
95 panic("asynchronous traps not implemented\n");
96
97 if (cpu->readMiscReg(IPR_SIRR)) {
98 for (int i = INTLEVEL_SOFTWARE_MIN;
99 i < INTLEVEL_SOFTWARE_MAX; i++) {
100 if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
101 // See table 4-19 of the 21164 hardware reference
102 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
103 summary |= (ULL(1) << i);
104 }
105 }
106 }
107
108 uint64_t interrupts = cpu->intr_status();
109
110 if (interrupts) {
111 for (int i = INTLEVEL_EXTERNAL_MIN;
112 i < INTLEVEL_EXTERNAL_MAX; i++) {
113 if (interrupts & (ULL(1) << i)) {
114 // See table 4-19 of the 21164 hardware reference
115 ipl = i;
116 summary |= (ULL(1) << i);
117 }
118 }
119 }
120
121 if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
122 cpu->setMiscReg(IPR_ISR, summary);
123 cpu->setMiscReg(IPR_INTID, ipl);
124 cpu->trap(new InterruptFault);
125 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
126 cpu->readMiscReg(IPR_IPLR), ipl, summary);
127 }
128
129}
130
131template <class CPU>
132void
133AlphaISA::zeroRegisters(CPU *cpu)
134{
135 // Insure ISA semantics
136 // (no longer very clean due to the change in setIntReg() in the
137 // cpu model. Consider changing later.)
138 cpu->cpuXC->setIntReg(ZeroReg, 0);
139 cpu->cpuXC->setFloatReg(ZeroReg, 0.0);
140}
141
142Fault
143CPUExecContext::hwrei()
144{
145 if (!inPalMode())
146 return new UnimplementedOpcodeFault;
147
148 setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
149
150 if (!misspeculating()) {
|
148 if (kernelStats)
149 kernelStats->hwrei();
| 151 cpu->kernelStats->hwrei();
|
150
151 cpu->checkInterrupts = true;
152 }
153
154 // FIXME: XXX check for interrupts? XXX
155 return NoFault;
156}
157
158int
159AlphaISA::MiscRegFile::getInstAsid()
160{
161 return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
162}
163
164int
165AlphaISA::MiscRegFile::getDataAsid()
166{
167 return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
168}
169
170AlphaISA::MiscReg
171AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
172{
173 uint64_t retval = 0; // return value, default 0
174
175 switch (idx) {
176 case AlphaISA::IPR_PALtemp0:
177 case AlphaISA::IPR_PALtemp1:
178 case AlphaISA::IPR_PALtemp2:
179 case AlphaISA::IPR_PALtemp3:
180 case AlphaISA::IPR_PALtemp4:
181 case AlphaISA::IPR_PALtemp5:
182 case AlphaISA::IPR_PALtemp6:
183 case AlphaISA::IPR_PALtemp7:
184 case AlphaISA::IPR_PALtemp8:
185 case AlphaISA::IPR_PALtemp9:
186 case AlphaISA::IPR_PALtemp10:
187 case AlphaISA::IPR_PALtemp11:
188 case AlphaISA::IPR_PALtemp12:
189 case AlphaISA::IPR_PALtemp13:
190 case AlphaISA::IPR_PALtemp14:
191 case AlphaISA::IPR_PALtemp15:
192 case AlphaISA::IPR_PALtemp16:
193 case AlphaISA::IPR_PALtemp17:
194 case AlphaISA::IPR_PALtemp18:
195 case AlphaISA::IPR_PALtemp19:
196 case AlphaISA::IPR_PALtemp20:
197 case AlphaISA::IPR_PALtemp21:
198 case AlphaISA::IPR_PALtemp22:
199 case AlphaISA::IPR_PALtemp23:
200 case AlphaISA::IPR_PAL_BASE:
201
202 case AlphaISA::IPR_IVPTBR:
203 case AlphaISA::IPR_DC_MODE:
204 case AlphaISA::IPR_MAF_MODE:
205 case AlphaISA::IPR_ISR:
206 case AlphaISA::IPR_EXC_ADDR:
207 case AlphaISA::IPR_IC_PERR_STAT:
208 case AlphaISA::IPR_DC_PERR_STAT:
209 case AlphaISA::IPR_MCSR:
210 case AlphaISA::IPR_ASTRR:
211 case AlphaISA::IPR_ASTER:
212 case AlphaISA::IPR_SIRR:
213 case AlphaISA::IPR_ICSR:
214 case AlphaISA::IPR_ICM:
215 case AlphaISA::IPR_DTB_CM:
216 case AlphaISA::IPR_IPLR:
217 case AlphaISA::IPR_INTID:
218 case AlphaISA::IPR_PMCTR:
219 // no side-effect
220 retval = ipr[idx];
221 break;
222
223 case AlphaISA::IPR_CC:
224 retval |= ipr[idx] & ULL(0xffffffff00000000);
225 retval |= xc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
226 break;
227
228 case AlphaISA::IPR_VA:
229 retval = ipr[idx];
230 break;
231
232 case AlphaISA::IPR_VA_FORM:
233 case AlphaISA::IPR_MM_STAT:
234 case AlphaISA::IPR_IFAULT_VA_FORM:
235 case AlphaISA::IPR_EXC_MASK:
236 case AlphaISA::IPR_EXC_SUM:
237 retval = ipr[idx];
238 break;
239
240 case AlphaISA::IPR_DTB_PTE:
241 {
242 AlphaISA::PTE &pte = xc->getDTBPtr()->index(!xc->misspeculating());
243
244 retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
245 retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
246 retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
247 retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
248 retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
249 retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
250 retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
251 }
252 break;
253
254 // write only registers
255 case AlphaISA::IPR_HWINT_CLR:
256 case AlphaISA::IPR_SL_XMIT:
257 case AlphaISA::IPR_DC_FLUSH:
258 case AlphaISA::IPR_IC_FLUSH:
259 case AlphaISA::IPR_ALT_MODE:
260 case AlphaISA::IPR_DTB_IA:
261 case AlphaISA::IPR_DTB_IAP:
262 case AlphaISA::IPR_ITB_IA:
263 case AlphaISA::IPR_ITB_IAP:
264 fault = new UnimplementedOpcodeFault;
265 break;
266
267 default:
268 // invalid IPR
269 fault = new UnimplementedOpcodeFault;
270 break;
271 }
272
273 return retval;
274}
275
276#ifdef DEBUG
277// Cause the simulator to break when changing to the following IPL
278int break_ipl = -1;
279#endif
280
281Fault
282AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
283{
284 uint64_t old;
285
286 if (xc->misspeculating())
287 return NoFault;
288
289 switch (idx) {
290 case AlphaISA::IPR_PALtemp0:
291 case AlphaISA::IPR_PALtemp1:
292 case AlphaISA::IPR_PALtemp2:
293 case AlphaISA::IPR_PALtemp3:
294 case AlphaISA::IPR_PALtemp4:
295 case AlphaISA::IPR_PALtemp5:
296 case AlphaISA::IPR_PALtemp6:
297 case AlphaISA::IPR_PALtemp7:
298 case AlphaISA::IPR_PALtemp8:
299 case AlphaISA::IPR_PALtemp9:
300 case AlphaISA::IPR_PALtemp10:
301 case AlphaISA::IPR_PALtemp11:
302 case AlphaISA::IPR_PALtemp12:
303 case AlphaISA::IPR_PALtemp13:
304 case AlphaISA::IPR_PALtemp14:
305 case AlphaISA::IPR_PALtemp15:
306 case AlphaISA::IPR_PALtemp16:
307 case AlphaISA::IPR_PALtemp17:
308 case AlphaISA::IPR_PALtemp18:
309 case AlphaISA::IPR_PALtemp19:
310 case AlphaISA::IPR_PALtemp20:
311 case AlphaISA::IPR_PALtemp21:
312 case AlphaISA::IPR_PALtemp22:
313 case AlphaISA::IPR_PAL_BASE:
314 case AlphaISA::IPR_IC_PERR_STAT:
315 case AlphaISA::IPR_DC_PERR_STAT:
316 case AlphaISA::IPR_PMCTR:
317 // write entire quad w/ no side-effect
318 ipr[idx] = val;
319 break;
320
321 case AlphaISA::IPR_CC_CTL:
322 // This IPR resets the cycle counter. We assume this only
323 // happens once... let's verify that.
324 assert(ipr[idx] == 0);
325 ipr[idx] = 1;
326 break;
327
328 case AlphaISA::IPR_CC:
329 // This IPR only writes the upper 64 bits. It's ok to write
330 // all 64 here since we mask out the lower 32 in rpcc (see
331 // isa_desc).
332 ipr[idx] = val;
333 break;
334
335 case AlphaISA::IPR_PALtemp23:
336 // write entire quad w/ no side-effect
337 old = ipr[idx];
338 ipr[idx] = val;
| 152
153 cpu->checkInterrupts = true;
154 }
155
156 // FIXME: XXX check for interrupts? XXX
157 return NoFault;
158}
159
160int
161AlphaISA::MiscRegFile::getInstAsid()
162{
163 return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
164}
165
166int
167AlphaISA::MiscRegFile::getDataAsid()
168{
169 return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
170}
171
172AlphaISA::MiscReg
173AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
174{
175 uint64_t retval = 0; // return value, default 0
176
177 switch (idx) {
178 case AlphaISA::IPR_PALtemp0:
179 case AlphaISA::IPR_PALtemp1:
180 case AlphaISA::IPR_PALtemp2:
181 case AlphaISA::IPR_PALtemp3:
182 case AlphaISA::IPR_PALtemp4:
183 case AlphaISA::IPR_PALtemp5:
184 case AlphaISA::IPR_PALtemp6:
185 case AlphaISA::IPR_PALtemp7:
186 case AlphaISA::IPR_PALtemp8:
187 case AlphaISA::IPR_PALtemp9:
188 case AlphaISA::IPR_PALtemp10:
189 case AlphaISA::IPR_PALtemp11:
190 case AlphaISA::IPR_PALtemp12:
191 case AlphaISA::IPR_PALtemp13:
192 case AlphaISA::IPR_PALtemp14:
193 case AlphaISA::IPR_PALtemp15:
194 case AlphaISA::IPR_PALtemp16:
195 case AlphaISA::IPR_PALtemp17:
196 case AlphaISA::IPR_PALtemp18:
197 case AlphaISA::IPR_PALtemp19:
198 case AlphaISA::IPR_PALtemp20:
199 case AlphaISA::IPR_PALtemp21:
200 case AlphaISA::IPR_PALtemp22:
201 case AlphaISA::IPR_PALtemp23:
202 case AlphaISA::IPR_PAL_BASE:
203
204 case AlphaISA::IPR_IVPTBR:
205 case AlphaISA::IPR_DC_MODE:
206 case AlphaISA::IPR_MAF_MODE:
207 case AlphaISA::IPR_ISR:
208 case AlphaISA::IPR_EXC_ADDR:
209 case AlphaISA::IPR_IC_PERR_STAT:
210 case AlphaISA::IPR_DC_PERR_STAT:
211 case AlphaISA::IPR_MCSR:
212 case AlphaISA::IPR_ASTRR:
213 case AlphaISA::IPR_ASTER:
214 case AlphaISA::IPR_SIRR:
215 case AlphaISA::IPR_ICSR:
216 case AlphaISA::IPR_ICM:
217 case AlphaISA::IPR_DTB_CM:
218 case AlphaISA::IPR_IPLR:
219 case AlphaISA::IPR_INTID:
220 case AlphaISA::IPR_PMCTR:
221 // no side-effect
222 retval = ipr[idx];
223 break;
224
225 case AlphaISA::IPR_CC:
226 retval |= ipr[idx] & ULL(0xffffffff00000000);
227 retval |= xc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
228 break;
229
230 case AlphaISA::IPR_VA:
231 retval = ipr[idx];
232 break;
233
234 case AlphaISA::IPR_VA_FORM:
235 case AlphaISA::IPR_MM_STAT:
236 case AlphaISA::IPR_IFAULT_VA_FORM:
237 case AlphaISA::IPR_EXC_MASK:
238 case AlphaISA::IPR_EXC_SUM:
239 retval = ipr[idx];
240 break;
241
242 case AlphaISA::IPR_DTB_PTE:
243 {
244 AlphaISA::PTE &pte = xc->getDTBPtr()->index(!xc->misspeculating());
245
246 retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
247 retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
248 retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
249 retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
250 retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
251 retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
252 retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
253 }
254 break;
255
256 // write only registers
257 case AlphaISA::IPR_HWINT_CLR:
258 case AlphaISA::IPR_SL_XMIT:
259 case AlphaISA::IPR_DC_FLUSH:
260 case AlphaISA::IPR_IC_FLUSH:
261 case AlphaISA::IPR_ALT_MODE:
262 case AlphaISA::IPR_DTB_IA:
263 case AlphaISA::IPR_DTB_IAP:
264 case AlphaISA::IPR_ITB_IA:
265 case AlphaISA::IPR_ITB_IAP:
266 fault = new UnimplementedOpcodeFault;
267 break;
268
269 default:
270 // invalid IPR
271 fault = new UnimplementedOpcodeFault;
272 break;
273 }
274
275 return retval;
276}
277
278#ifdef DEBUG
279// Cause the simulator to break when changing to the following IPL
280int break_ipl = -1;
281#endif
282
283Fault
284AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
285{
286 uint64_t old;
287
288 if (xc->misspeculating())
289 return NoFault;
290
291 switch (idx) {
292 case AlphaISA::IPR_PALtemp0:
293 case AlphaISA::IPR_PALtemp1:
294 case AlphaISA::IPR_PALtemp2:
295 case AlphaISA::IPR_PALtemp3:
296 case AlphaISA::IPR_PALtemp4:
297 case AlphaISA::IPR_PALtemp5:
298 case AlphaISA::IPR_PALtemp6:
299 case AlphaISA::IPR_PALtemp7:
300 case AlphaISA::IPR_PALtemp8:
301 case AlphaISA::IPR_PALtemp9:
302 case AlphaISA::IPR_PALtemp10:
303 case AlphaISA::IPR_PALtemp11:
304 case AlphaISA::IPR_PALtemp12:
305 case AlphaISA::IPR_PALtemp13:
306 case AlphaISA::IPR_PALtemp14:
307 case AlphaISA::IPR_PALtemp15:
308 case AlphaISA::IPR_PALtemp16:
309 case AlphaISA::IPR_PALtemp17:
310 case AlphaISA::IPR_PALtemp18:
311 case AlphaISA::IPR_PALtemp19:
312 case AlphaISA::IPR_PALtemp20:
313 case AlphaISA::IPR_PALtemp21:
314 case AlphaISA::IPR_PALtemp22:
315 case AlphaISA::IPR_PAL_BASE:
316 case AlphaISA::IPR_IC_PERR_STAT:
317 case AlphaISA::IPR_DC_PERR_STAT:
318 case AlphaISA::IPR_PMCTR:
319 // write entire quad w/ no side-effect
320 ipr[idx] = val;
321 break;
322
323 case AlphaISA::IPR_CC_CTL:
324 // This IPR resets the cycle counter. We assume this only
325 // happens once... let's verify that.
326 assert(ipr[idx] == 0);
327 ipr[idx] = 1;
328 break;
329
330 case AlphaISA::IPR_CC:
331 // This IPR only writes the upper 64 bits. It's ok to write
332 // all 64 here since we mask out the lower 32 in rpcc (see
333 // isa_desc).
334 ipr[idx] = val;
335 break;
336
337 case AlphaISA::IPR_PALtemp23:
338 // write entire quad w/ no side-effect
339 old = ipr[idx];
340 ipr[idx] = val;
|
339 if (xc->getKernelStats())
340 xc->getKernelStats()->context(old, val, xc);
| 341 xc->getCpuPtr()->kernelStats->context(old, val, xc);
|
341 break;
342
343 case AlphaISA::IPR_DTB_PTE:
344 // write entire quad w/ no side-effect, tag is forthcoming
345 ipr[idx] = val;
346 break;
347
348 case AlphaISA::IPR_EXC_ADDR:
349 // second least significant bit in PC is always zero
350 ipr[idx] = val & ~2;
351 break;
352
353 case AlphaISA::IPR_ASTRR:
354 case AlphaISA::IPR_ASTER:
355 // only write least significant four bits - privilege mask
356 ipr[idx] = val & 0xf;
357 break;
358
359 case AlphaISA::IPR_IPLR:
360#ifdef DEBUG
361 if (break_ipl != -1 && break_ipl == (val & 0x1f))
362 debug_break();
363#endif
364
365 // only write least significant five bits - interrupt level
366 ipr[idx] = val & 0x1f;
| 342 break;
343
344 case AlphaISA::IPR_DTB_PTE:
345 // write entire quad w/ no side-effect, tag is forthcoming
346 ipr[idx] = val;
347 break;
348
349 case AlphaISA::IPR_EXC_ADDR:
350 // second least significant bit in PC is always zero
351 ipr[idx] = val & ~2;
352 break;
353
354 case AlphaISA::IPR_ASTRR:
355 case AlphaISA::IPR_ASTER:
356 // only write least significant four bits - privilege mask
357 ipr[idx] = val & 0xf;
358 break;
359
360 case AlphaISA::IPR_IPLR:
361#ifdef DEBUG
362 if (break_ipl != -1 && break_ipl == (val & 0x1f))
363 debug_break();
364#endif
365
366 // only write least significant five bits - interrupt level
367 ipr[idx] = val & 0x1f;
|
367 if (xc->getKernelStats())
368 xc->getKernelStats()->swpipl(ipr[idx]);
| 368 xc->getCpuPtr()->kernelStats->swpipl(ipr[idx]);
|
369 break;
370
371 case AlphaISA::IPR_DTB_CM:
| 369 break;
370
371 case AlphaISA::IPR_DTB_CM:
|
372 if (val & 0x18) {
373 if (xc->getKernelStats())
374 xc->getKernelStats()->mode(Kernel::user, xc);
375 } else {
376 if (xc->getKernelStats())
377 xc->getKernelStats()->mode(Kernel::kernel, xc);
378 }
| 372 if (val & 0x18)
373 xc->getCpuPtr()->kernelStats->mode(Kernel::user, xc);
374 else
375 xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc);
|
379
380 case AlphaISA::IPR_ICM:
381 // only write two mode bits - processor mode
382 ipr[idx] = val & 0x18;
383 break;
384
385 case AlphaISA::IPR_ALT_MODE:
386 // only write two mode bits - processor mode
387 ipr[idx] = val & 0x18;
388 break;
389
390 case AlphaISA::IPR_MCSR:
391 // more here after optimization...
392 ipr[idx] = val;
393 break;
394
395 case AlphaISA::IPR_SIRR:
396 // only write software interrupt mask
397 ipr[idx] = val & 0x7fff0;
398 break;
399
400 case AlphaISA::IPR_ICSR:
401 ipr[idx] = val & ULL(0xffffff0300);
402 break;
403
404 case AlphaISA::IPR_IVPTBR:
405 case AlphaISA::IPR_MVPTBR:
406 ipr[idx] = val & ULL(0xffffffffc0000000);
407 break;
408
409 case AlphaISA::IPR_DC_TEST_CTL:
410 ipr[idx] = val & 0x1ffb;
411 break;
412
413 case AlphaISA::IPR_DC_MODE:
414 case AlphaISA::IPR_MAF_MODE:
415 ipr[idx] = val & 0x3f;
416 break;
417
418 case AlphaISA::IPR_ITB_ASN:
419 ipr[idx] = val & 0x7f0;
420 break;
421
422 case AlphaISA::IPR_DTB_ASN:
423 ipr[idx] = val & ULL(0xfe00000000000000);
424 break;
425
426 case AlphaISA::IPR_EXC_SUM:
427 case AlphaISA::IPR_EXC_MASK:
428 // any write to this register clears it
429 ipr[idx] = 0;
430 break;
431
432 case AlphaISA::IPR_INTID:
433 case AlphaISA::IPR_SL_RCV:
434 case AlphaISA::IPR_MM_STAT:
435 case AlphaISA::IPR_ITB_PTE_TEMP:
436 case AlphaISA::IPR_DTB_PTE_TEMP:
437 // read-only registers
438 return new UnimplementedOpcodeFault;
439
440 case AlphaISA::IPR_HWINT_CLR:
441 case AlphaISA::IPR_SL_XMIT:
442 case AlphaISA::IPR_DC_FLUSH:
443 case AlphaISA::IPR_IC_FLUSH:
444 // the following are write only
445 ipr[idx] = val;
446 break;
447
448 case AlphaISA::IPR_DTB_IA:
449 // really a control write
450 ipr[idx] = 0;
451
452 xc->getDTBPtr()->flushAll();
453 break;
454
455 case AlphaISA::IPR_DTB_IAP:
456 // really a control write
457 ipr[idx] = 0;
458
459 xc->getDTBPtr()->flushProcesses();
460 break;
461
462 case AlphaISA::IPR_DTB_IS:
463 // really a control write
464 ipr[idx] = val;
465
466 xc->getDTBPtr()->flushAddr(val,
467 DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
468 break;
469
470 case AlphaISA::IPR_DTB_TAG: {
471 struct AlphaISA::PTE pte;
472
473 // FIXME: granularity hints NYI...
474 if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
475 panic("PTE GH field != 0");
476
477 // write entire quad
478 ipr[idx] = val;
479
480 // construct PTE for new entry
481 pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
482 pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
483 pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
484 pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
485 pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
486 pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
487 pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
488
489 // insert new TAG/PTE value into data TLB
490 xc->getDTBPtr()->insert(val, pte);
491 }
492 break;
493
494 case AlphaISA::IPR_ITB_PTE: {
495 struct AlphaISA::PTE pte;
496
497 // FIXME: granularity hints NYI...
498 if (ITB_PTE_GH(val) != 0)
499 panic("PTE GH field != 0");
500
501 // write entire quad
502 ipr[idx] = val;
503
504 // construct PTE for new entry
505 pte.ppn = ITB_PTE_PPN(val);
506 pte.xre = ITB_PTE_XRE(val);
507 pte.xwe = 0;
508 pte.fonr = ITB_PTE_FONR(val);
509 pte.fonw = ITB_PTE_FONW(val);
510 pte.asma = ITB_PTE_ASMA(val);
511 pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
512
513 // insert new TAG/PTE value into data TLB
514 xc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
515 }
516 break;
517
518 case AlphaISA::IPR_ITB_IA:
519 // really a control write
520 ipr[idx] = 0;
521
522 xc->getITBPtr()->flushAll();
523 break;
524
525 case AlphaISA::IPR_ITB_IAP:
526 // really a control write
527 ipr[idx] = 0;
528
529 xc->getITBPtr()->flushProcesses();
530 break;
531
532 case AlphaISA::IPR_ITB_IS:
533 // really a control write
534 ipr[idx] = val;
535
536 xc->getITBPtr()->flushAddr(val,
537 ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
538 break;
539
540 default:
541 // invalid IPR
542 return new UnimplementedOpcodeFault;
543 }
544
545 // no error...
546 return NoFault;
547}
548
549void
550AlphaISA::copyIprs(ExecContext *src, ExecContext *dest)
551{
552 for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
553 dest->setMiscReg(i, src->readMiscReg(i));
554 }
555}
556
557/**
558 * Check for special simulator handling of specific PAL calls.
559 * If return value is false, actual PAL call will be suppressed.
560 */
561bool
562CPUExecContext::simPalCheck(int palFunc)
563{
| 376
377 case AlphaISA::IPR_ICM:
378 // only write two mode bits - processor mode
379 ipr[idx] = val & 0x18;
380 break;
381
382 case AlphaISA::IPR_ALT_MODE:
383 // only write two mode bits - processor mode
384 ipr[idx] = val & 0x18;
385 break;
386
387 case AlphaISA::IPR_MCSR:
388 // more here after optimization...
389 ipr[idx] = val;
390 break;
391
392 case AlphaISA::IPR_SIRR:
393 // only write software interrupt mask
394 ipr[idx] = val & 0x7fff0;
395 break;
396
397 case AlphaISA::IPR_ICSR:
398 ipr[idx] = val & ULL(0xffffff0300);
399 break;
400
401 case AlphaISA::IPR_IVPTBR:
402 case AlphaISA::IPR_MVPTBR:
403 ipr[idx] = val & ULL(0xffffffffc0000000);
404 break;
405
406 case AlphaISA::IPR_DC_TEST_CTL:
407 ipr[idx] = val & 0x1ffb;
408 break;
409
410 case AlphaISA::IPR_DC_MODE:
411 case AlphaISA::IPR_MAF_MODE:
412 ipr[idx] = val & 0x3f;
413 break;
414
415 case AlphaISA::IPR_ITB_ASN:
416 ipr[idx] = val & 0x7f0;
417 break;
418
419 case AlphaISA::IPR_DTB_ASN:
420 ipr[idx] = val & ULL(0xfe00000000000000);
421 break;
422
423 case AlphaISA::IPR_EXC_SUM:
424 case AlphaISA::IPR_EXC_MASK:
425 // any write to this register clears it
426 ipr[idx] = 0;
427 break;
428
429 case AlphaISA::IPR_INTID:
430 case AlphaISA::IPR_SL_RCV:
431 case AlphaISA::IPR_MM_STAT:
432 case AlphaISA::IPR_ITB_PTE_TEMP:
433 case AlphaISA::IPR_DTB_PTE_TEMP:
434 // read-only registers
435 return new UnimplementedOpcodeFault;
436
437 case AlphaISA::IPR_HWINT_CLR:
438 case AlphaISA::IPR_SL_XMIT:
439 case AlphaISA::IPR_DC_FLUSH:
440 case AlphaISA::IPR_IC_FLUSH:
441 // the following are write only
442 ipr[idx] = val;
443 break;
444
445 case AlphaISA::IPR_DTB_IA:
446 // really a control write
447 ipr[idx] = 0;
448
449 xc->getDTBPtr()->flushAll();
450 break;
451
452 case AlphaISA::IPR_DTB_IAP:
453 // really a control write
454 ipr[idx] = 0;
455
456 xc->getDTBPtr()->flushProcesses();
457 break;
458
459 case AlphaISA::IPR_DTB_IS:
460 // really a control write
461 ipr[idx] = val;
462
463 xc->getDTBPtr()->flushAddr(val,
464 DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
465 break;
466
467 case AlphaISA::IPR_DTB_TAG: {
468 struct AlphaISA::PTE pte;
469
470 // FIXME: granularity hints NYI...
471 if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
472 panic("PTE GH field != 0");
473
474 // write entire quad
475 ipr[idx] = val;
476
477 // construct PTE for new entry
478 pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
479 pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
480 pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
481 pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
482 pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
483 pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
484 pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
485
486 // insert new TAG/PTE value into data TLB
487 xc->getDTBPtr()->insert(val, pte);
488 }
489 break;
490
491 case AlphaISA::IPR_ITB_PTE: {
492 struct AlphaISA::PTE pte;
493
494 // FIXME: granularity hints NYI...
495 if (ITB_PTE_GH(val) != 0)
496 panic("PTE GH field != 0");
497
498 // write entire quad
499 ipr[idx] = val;
500
501 // construct PTE for new entry
502 pte.ppn = ITB_PTE_PPN(val);
503 pte.xre = ITB_PTE_XRE(val);
504 pte.xwe = 0;
505 pte.fonr = ITB_PTE_FONR(val);
506 pte.fonw = ITB_PTE_FONW(val);
507 pte.asma = ITB_PTE_ASMA(val);
508 pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
509
510 // insert new TAG/PTE value into data TLB
511 xc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
512 }
513 break;
514
515 case AlphaISA::IPR_ITB_IA:
516 // really a control write
517 ipr[idx] = 0;
518
519 xc->getITBPtr()->flushAll();
520 break;
521
522 case AlphaISA::IPR_ITB_IAP:
523 // really a control write
524 ipr[idx] = 0;
525
526 xc->getITBPtr()->flushProcesses();
527 break;
528
529 case AlphaISA::IPR_ITB_IS:
530 // really a control write
531 ipr[idx] = val;
532
533 xc->getITBPtr()->flushAddr(val,
534 ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
535 break;
536
537 default:
538 // invalid IPR
539 return new UnimplementedOpcodeFault;
540 }
541
542 // no error...
543 return NoFault;
544}
545
546void
547AlphaISA::copyIprs(ExecContext *src, ExecContext *dest)
548{
549 for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
550 dest->setMiscReg(i, src->readMiscReg(i));
551 }
552}
553
554/**
555 * Check for special simulator handling of specific PAL calls.
556 * If return value is false, actual PAL call will be suppressed.
557 */
558bool
559CPUExecContext::simPalCheck(int palFunc)
560{
|
564 if (kernelStats)
565 kernelStats->callpal(palFunc, proxy);
| 561 cpu->kernelStats->callpal(palFunc, proxy);
|
566
567 switch (palFunc) {
568 case PAL::halt:
569 halt();
570 if (--System::numSystemsRunning == 0)
571 new SimExitEvent("all cpus halted");
572 break;
573
574 case PAL::bpt:
575 case PAL::bugchk:
576 if (system->breakpoint())
577 return false;
578 break;
579 }
580
581 return true;
582}
583
584#endif // FULL_SYSTEM
| 562
563 switch (palFunc) {
564 case PAL::halt:
565 halt();
566 if (--System::numSystemsRunning == 0)
567 new SimExitEvent("all cpus halted");
568 break;
569
570 case PAL::bpt:
571 case PAL::bugchk:
572 if (system->breakpoint())
573 return false;
574 break;
575 }
576
577 return true;
578}
579
580#endif // FULL_SYSTEM
|