1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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197}
198
199// Cause the simulator to break when changing to the following IPL
200int break_ipl = -1;
201
202void
203ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
204{
205 uint64_t old;
206
207 if (tc->misspeculating())
208 return;
209
210 switch (idx) {
211 case IPR_PALtemp0:
212 case IPR_PALtemp1:
213 case IPR_PALtemp2:
214 case IPR_PALtemp3:

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250 // This IPR only writes the upper 64 bits. It's ok to write
251 // all 64 here since we mask out the lower 32 in rpcc (see
252 // isa_desc).
253 ipr[idx] = val;
254 break;
255
256 case IPR_PALtemp23:
257 // write entire quad w/ no side-effect
258 old = ipr[idx];
259 ipr[idx] = val;
260 if (tc->getKernelStats())
261 tc->getKernelStats()->context(old, val, tc);
262 break;
263
264 case IPR_DTB_PTE:
265 // write entire quad w/ no side-effect, tag is forthcoming
266 ipr[idx] = val;
267 break;
268
269 case IPR_EXC_ADDR:

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