1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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89void
90AlphaISA::processInterrupts(CPU *cpu)
91{
92 //Check if there are any outstanding interrupts
93 //Handle the interrupts
94 int ipl = 0;
95 int summary = 0;
96
97 cpu->checkInterrupts = false;
98
99 if (cpu->readMiscReg(IPR_ASTRR))
100 panic("asynchronous traps not implemented\n");
101
102 if (cpu->readMiscReg(IPR_SIRR)) {
103 for (int i = INTLEVEL_SOFTWARE_MIN;
104 i < INTLEVEL_SOFTWARE_MAX; i++) {
105 if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
106 // See table 4-19 of the 21164 hardware reference

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150 if (!(readPC() & 0x3))
151 return new UnimplementedOpcodeFault;
152
153 setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
154
155 if (!misspeculating()) {
156 if (kernelStats)
157 kernelStats->hwrei();
158
159 cpu->checkInterrupts = true;
160 }
161
162 // FIXME: XXX check for interrupts? XXX
163 return NoFault;
164}
165
166int
167AlphaISA::MiscRegFile::getInstAsid()

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