1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
43#include "sim/sim_exit.hh"
44
45namespace AlphaISA {
46
47////////////////////////////////////////////////////////////////////////
48//
49// Machine dependent functions
50//
51void
52initCPU(ThreadContext *tc, int cpuId)
53{
54 initIPRs(tc, cpuId);

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69{
70 // Insure ISA semantics
71 // (no longer very clean due to the change in setIntReg() in the
72 // cpu model. Consider changing later.)
73 cpu->thread->setIntReg(ZeroReg, 0);
74 cpu->thread->setFloatReg(ZeroReg, 0.0);
75}
76
77////////////////////////////////////////////////////////////////////////
78//
79//
80//
81void
82initIPRs(ThreadContext *tc, int cpuId)
83{
84 for (int i = 0; i < NumInternalProcRegs; ++i) {

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192 // invalid IPR
193 panic("Tried to read from invalid ipr %d\n", idx);
194 break;
195 }
196
197 return retval;
198}
199
200// Cause the simulator to break when changing to the following IPL
201int break_ipl = -1;
202
203void
204ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
205{
206 uint64_t old;
207
208 if (tc->misspeculating())
209 return;
210
211 switch (idx) {
212 case IPR_PALtemp0:
213 case IPR_PALtemp1:
214 case IPR_PALtemp2:
215 case IPR_PALtemp3:

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251 // This IPR only writes the upper 64 bits. It's ok to write
252 // all 64 here since we mask out the lower 32 in rpcc (see
253 // isa_desc).
254 ipr[idx] = val;
255 break;
256
257 case IPR_PALtemp23:
258 // write entire quad w/ no side-effect
259 old = ipr[idx];
260 ipr[idx] = val;
261 if (tc->getKernelStats())
262 tc->getKernelStats()->context(old, val, tc);
263 break;
264
265 case IPR_DTB_PTE:
266 // write entire quad w/ no side-effect, tag is forthcoming
267 ipr[idx] = val;
268 break;
269
270 case IPR_EXC_ADDR:

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281 case IPR_IPLR:
282#ifdef DEBUG
283 if (break_ipl != -1 && break_ipl == (int)(val & 0x1f))
284 Debug::breakpoint();
285#endif
286
287 // only write least significant five bits - interrupt level
288 ipr[idx] = val & 0x1f;
289 if (tc->getKernelStats())
290 tc->getKernelStats()->swpipl(ipr[idx]);
291 break;
292
293 case IPR_DTB_CM:
294 if (val & 0x18) {
295 if (tc->getKernelStats())
296 tc->getKernelStats()->mode(Kernel::user, tc);
297 } else {
298 if (tc->getKernelStats())
299 tc->getKernelStats()->mode(Kernel::kernel, tc);
300 }
301
302 case IPR_ICM:
303 // only write two mode bits - processor mode
304 ipr[idx] = val & 0x18;
305 break;
306
307 case IPR_ALT_MODE:
308 // only write two mode bits - processor mode

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469copyIprs(ThreadContext *src, ThreadContext *dest)
470{
471 for (int i = 0; i < NumInternalProcRegs; ++i)
472 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
473}
474
475} // namespace AlphaISA
476
477using namespace AlphaISA;
478
479Fault
480SimpleThread::hwrei()
481{
482 PCState pc = pcState();
483 if (!(pc.pc() & 0x3))
484 return new UnimplementedOpcodeFault;

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518 case PAL::bugchk:
519 if (system->breakpoint())
520 return false;
521 break;
522 }
523
524 return true;
525}