1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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39#include "base/stats/events.hh"
40#include "config/full_system.hh"
41#include "cpu/base.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"
44#include "sim/debug.hh"
45#include "sim/sim_exit.hh"
46
47namespace AlphaISA {
48
49#if FULL_SYSTEM
50
51////////////////////////////////////////////////////////////////////////
52//
53// Machine dependent functions
54//
55void
56initCPU(ThreadContext *tc, int cpuId)
57{
58 initIPRs(tc, cpuId);
59
60 tc->setIntReg(16, cpuId);
61 tc->setIntReg(0, cpuId);
62
63 AlphaFault *reset = new ResetFault;
64
65 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
66 tc->setNextPC(tc->readPC() + sizeof(MachInst));
67
68 delete reset;
69}
70
71
72template <class CPU>
73void
74processInterrupts(CPU *cpu)
75{
76 //Check if there are any outstanding interrupts
77 //Handle the interrupts
78 int ipl = 0;
79 int summary = 0;
80
81 if (cpu->readMiscRegNoEffect(IPR_ASTRR))
82 panic("asynchronous traps not implemented\n");

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112 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
113 cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
114 }
115
116}
117
118template <class CPU>
119void
120zeroRegisters(CPU *cpu)
121{
122 // Insure ISA semantics
123 // (no longer very clean due to the change in setIntReg() in the
124 // cpu model. Consider changing later.)
125 cpu->thread->setIntReg(ZeroReg, 0);
126 cpu->thread->setFloatReg(ZeroReg, 0.0);
127}
128
129int
130MiscRegFile::getInstAsid()
131{
132 return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
133}
134
135int
136MiscRegFile::getDataAsid()
137{
138 return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
139}
140
141#endif
142
143////////////////////////////////////////////////////////////////////////
144//
145//
146//
147void
148initIPRs(ThreadContext *tc, int cpuId)
149{
150 for (int i = 0; i < NumInternalProcRegs; ++i) {
151 tc->setMiscRegNoEffect(i, 0);
152 }
153
154 tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
155 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
156 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
157}
158
159MiscReg
160MiscRegFile::readIpr(int idx, ThreadContext *tc)
161{
162 uint64_t retval = 0; // return value, default 0
163
164 switch (idx) {
165 case IPR_PALtemp0:
166 case IPR_PALtemp1:
167 case IPR_PALtemp2:
168 case IPR_PALtemp3:
169 case IPR_PALtemp4:
170 case IPR_PALtemp5:
171 case IPR_PALtemp6:
172 case IPR_PALtemp7:
173 case IPR_PALtemp8:
174 case IPR_PALtemp9:
175 case IPR_PALtemp10:
176 case IPR_PALtemp11:
177 case IPR_PALtemp12:
178 case IPR_PALtemp13:
179 case IPR_PALtemp14:
180 case IPR_PALtemp15:
181 case IPR_PALtemp16:
182 case IPR_PALtemp17:
183 case IPR_PALtemp18:
184 case IPR_PALtemp19:
185 case IPR_PALtemp20:
186 case IPR_PALtemp21:
187 case IPR_PALtemp22:
188 case IPR_PALtemp23:
189 case IPR_PAL_BASE:
190
191 case IPR_IVPTBR:
192 case IPR_DC_MODE:
193 case IPR_MAF_MODE:
194 case IPR_ISR:
195 case IPR_EXC_ADDR:
196 case IPR_IC_PERR_STAT:
197 case IPR_DC_PERR_STAT:
198 case IPR_MCSR:
199 case IPR_ASTRR:
200 case IPR_ASTER:
201 case IPR_SIRR:
202 case IPR_ICSR:
203 case IPR_ICM:
204 case IPR_DTB_CM:
205 case IPR_IPLR:
206 case IPR_INTID:
207 case IPR_PMCTR:
208 // no side-effect
209 retval = ipr[idx];
210 break;
211
212 case IPR_CC:
213 retval |= ipr[idx] & ULL(0xffffffff00000000);
214 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
215 break;
216
217 case IPR_VA:
218 retval = ipr[idx];
219 break;
220
221 case IPR_VA_FORM:
222 case IPR_MM_STAT:
223 case IPR_IFAULT_VA_FORM:
224 case IPR_EXC_MASK:
225 case IPR_EXC_SUM:
226 retval = ipr[idx];
227 break;
228
229 case IPR_DTB_PTE:
230 {
231 TlbEntry &entry
232 = tc->getDTBPtr()->index(!tc->misspeculating());
233
234 retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
235 retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
236 retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12;
237 retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1;
238 retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2;
239 retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4;
240 retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57;
241 }
242 break;
243
244 // write only registers
245 case IPR_HWINT_CLR:
246 case IPR_SL_XMIT:
247 case IPR_DC_FLUSH:
248 case IPR_IC_FLUSH:
249 case IPR_ALT_MODE:
250 case IPR_DTB_IA:
251 case IPR_DTB_IAP:
252 case IPR_ITB_IA:
253 case IPR_ITB_IAP:
254 panic("Tried to read write only register %d\n", idx);
255 break;
256
257 default:
258 // invalid IPR
259 panic("Tried to read from invalid ipr %d\n", idx);
260 break;
261 }
262
263 return retval;
264}
265
266#ifdef DEBUG
267// Cause the simulator to break when changing to the following IPL
268int break_ipl = -1;
269#endif
270
271void
272MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
273{
274 uint64_t old;
275
276 if (tc->misspeculating())
277 return;
278
279 switch (idx) {
280 case IPR_PALtemp0:
281 case IPR_PALtemp1:
282 case IPR_PALtemp2:
283 case IPR_PALtemp3:
284 case IPR_PALtemp4:
285 case IPR_PALtemp5:
286 case IPR_PALtemp6:
287 case IPR_PALtemp7:
288 case IPR_PALtemp8:
289 case IPR_PALtemp9:
290 case IPR_PALtemp10:
291 case IPR_PALtemp11:
292 case IPR_PALtemp12:
293 case IPR_PALtemp13:
294 case IPR_PALtemp14:
295 case IPR_PALtemp15:
296 case IPR_PALtemp16:
297 case IPR_PALtemp17:
298 case IPR_PALtemp18:
299 case IPR_PALtemp19:
300 case IPR_PALtemp20:
301 case IPR_PALtemp21:
302 case IPR_PALtemp22:
303 case IPR_PAL_BASE:
304 case IPR_IC_PERR_STAT:
305 case IPR_DC_PERR_STAT:
306 case IPR_PMCTR:
307 // write entire quad w/ no side-effect
308 ipr[idx] = val;
309 break;
310
311 case IPR_CC_CTL:
312 // This IPR resets the cycle counter. We assume this only
313 // happens once... let's verify that.
314 assert(ipr[idx] == 0);
315 ipr[idx] = 1;
316 break;
317
318 case IPR_CC:
319 // This IPR only writes the upper 64 bits. It's ok to write
320 // all 64 here since we mask out the lower 32 in rpcc (see
321 // isa_desc).
322 ipr[idx] = val;
323 break;
324
325 case IPR_PALtemp23:
326 // write entire quad w/ no side-effect
327 old = ipr[idx];
328 ipr[idx] = val;
329#if FULL_SYSTEM
330 if (tc->getKernelStats())
331 tc->getKernelStats()->context(old, val, tc);
332#endif
333 break;
334
335 case IPR_DTB_PTE:
336 // write entire quad w/ no side-effect, tag is forthcoming
337 ipr[idx] = val;
338 break;
339
340 case IPR_EXC_ADDR:
341 // second least significant bit in PC is always zero
342 ipr[idx] = val & ~2;
343 break;
344
345 case IPR_ASTRR:
346 case IPR_ASTER:
347 // only write least significant four bits - privilege mask
348 ipr[idx] = val & 0xf;
349 break;
350
351 case IPR_IPLR:
352#ifdef DEBUG
353 if (break_ipl != -1 && break_ipl == (val & 0x1f))
354 debug_break();
355#endif
356
357 // only write least significant five bits - interrupt level
358 ipr[idx] = val & 0x1f;
359#if FULL_SYSTEM
360 if (tc->getKernelStats())
361 tc->getKernelStats()->swpipl(ipr[idx]);
362#endif
363 break;
364
365 case IPR_DTB_CM:
366#if FULL_SYSTEM
367 if (val & 0x18) {
368 if (tc->getKernelStats())
369 tc->getKernelStats()->mode(Kernel::user, tc);
370 } else {
371 if (tc->getKernelStats())
372 tc->getKernelStats()->mode(Kernel::kernel, tc);
373 }
374#endif
375
376 case IPR_ICM:
377 // only write two mode bits - processor mode
378 ipr[idx] = val & 0x18;
379 break;
380
381 case IPR_ALT_MODE:
382 // only write two mode bits - processor mode
383 ipr[idx] = val & 0x18;
384 break;
385
386 case IPR_MCSR:
387 // more here after optimization...
388 ipr[idx] = val;
389 break;
390
391 case IPR_SIRR:
392 // only write software interrupt mask
393 ipr[idx] = val & 0x7fff0;
394 break;
395
396 case IPR_ICSR:
397 ipr[idx] = val & ULL(0xffffff0300);
398 break;
399
400 case IPR_IVPTBR:
401 case IPR_MVPTBR:
402 ipr[idx] = val & ULL(0xffffffffc0000000);
403 break;
404
405 case IPR_DC_TEST_CTL:
406 ipr[idx] = val & 0x1ffb;
407 break;
408
409 case IPR_DC_MODE:
410 case IPR_MAF_MODE:
411 ipr[idx] = val & 0x3f;
412 break;
413
414 case IPR_ITB_ASN:
415 ipr[idx] = val & 0x7f0;
416 break;
417
418 case IPR_DTB_ASN:
419 ipr[idx] = val & ULL(0xfe00000000000000);
420 break;
421
422 case IPR_EXC_SUM:
423 case IPR_EXC_MASK:
424 // any write to this register clears it
425 ipr[idx] = 0;
426 break;
427
428 case IPR_INTID:
429 case IPR_SL_RCV:
430 case IPR_MM_STAT:
431 case IPR_ITB_PTE_TEMP:
432 case IPR_DTB_PTE_TEMP:
433 // read-only registers
434 panic("Tried to write read only ipr %d\n", idx);
435
436 case IPR_HWINT_CLR:
437 case IPR_SL_XMIT:
438 case IPR_DC_FLUSH:
439 case IPR_IC_FLUSH:
440 // the following are write only
441 ipr[idx] = val;
442 break;
443
444 case IPR_DTB_IA:
445 // really a control write
446 ipr[idx] = 0;
447
448 tc->getDTBPtr()->flushAll();
449 break;
450
451 case IPR_DTB_IAP:
452 // really a control write
453 ipr[idx] = 0;
454
455 tc->getDTBPtr()->flushProcesses();
456 break;
457
458 case IPR_DTB_IS:
459 // really a control write
460 ipr[idx] = val;
461
462 tc->getDTBPtr()->flushAddr(val,
463 DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
464 break;
465
466 case IPR_DTB_TAG: {
467 struct TlbEntry entry;
468
469 // FIXME: granularity hints NYI...
470 if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
471 panic("PTE GH field != 0");
472
473 // write entire quad
474 ipr[idx] = val;
475
476 // construct PTE for new entry
477 entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]);
478 entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]);
479 entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]);
480 entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]);
481 entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]);
482 entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]);
483 entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
484
485 // insert new TAG/PTE value into data TLB
486 tc->getDTBPtr()->insert(val, entry);
487 }
488 break;
489
490 case IPR_ITB_PTE: {
491 struct TlbEntry entry;
492
493 // FIXME: granularity hints NYI...
494 if (ITB_PTE_GH(val) != 0)
495 panic("PTE GH field != 0");
496
497 // write entire quad
498 ipr[idx] = val;
499
500 // construct PTE for new entry
501 entry.ppn = ITB_PTE_PPN(val);
502 entry.xre = ITB_PTE_XRE(val);
503 entry.xwe = 0;
504 entry.fonr = ITB_PTE_FONR(val);
505 entry.fonw = ITB_PTE_FONW(val);
506 entry.asma = ITB_PTE_ASMA(val);
507 entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
508
509 // insert new TAG/PTE value into data TLB
510 tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry);
511 }
512 break;
513
514 case IPR_ITB_IA:
515 // really a control write
516 ipr[idx] = 0;
517
518 tc->getITBPtr()->flushAll();
519 break;
520
521 case IPR_ITB_IAP:
522 // really a control write
523 ipr[idx] = 0;
524
525 tc->getITBPtr()->flushProcesses();
526 break;
527
528 case IPR_ITB_IS:
529 // really a control write
530 ipr[idx] = val;
531
532 tc->getITBPtr()->flushAddr(val,
533 ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
534 break;
535
536 default:
537 // invalid IPR
538 panic("Tried to write to invalid ipr %d\n", idx);
539 }
540
541 // no error...
542}
543
544
545void
546copyIprs(ThreadContext *src, ThreadContext *dest)
547{
548 for (int i = 0; i < NumInternalProcRegs; ++i) {
549 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
550 }
551}
552
553} // namespace AlphaISA
554
555#if FULL_SYSTEM
556using namespace AlphaISA;
557
558Fault
559SimpleThread::hwrei()
560{
561 if (!(readPC() & 0x3))
562 return new UnimplementedOpcodeFault;
563
564 setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
565
566 if (!misspeculating()) {
567 if (kernelStats)
568 kernelStats->hwrei();
569 }
570
571 // FIXME: XXX check for interrupts? XXX
572 return NoFault;
573}
574
575/**
576 * Check for special simulator handling of specific PAL calls.
577 * If return value is false, actual PAL call will be suppressed.
578 */
579bool
580SimpleThread::simPalCheck(int palFunc)
581{
582 if (kernelStats)

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