1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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63 AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
64
65 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
66 tc->setNextPC(tc->readPC() + sizeof(MachInst));
67
68 delete reset;
69}
70
71
72template <class CPU>
73void
74AlphaISA::processInterrupts(CPU *cpu)
75{
76 //Check if there are any outstanding interrupts
77 //Handle the interrupts
78 int ipl = 0;
79 int summary = 0;

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150}
151
152int
153AlphaISA::MiscRegFile::getDataAsid()
154{
155 return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
156}
157
158#endif
159
160////////////////////////////////////////////////////////////////////////
161//
162//
163//
164void
165AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
166{
167 for (int i = 0; i < NumInternalProcRegs; ++i) {
168 tc->setMiscRegNoEffect(i, 0);
169 }
170
171 tc->setMiscRegNoEffect(IPR_PAL_BASE, EV5::PalBase);
172 tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
173 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
174}
175
176AlphaISA::MiscReg
177AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
178{
179 uint64_t retval = 0; // return value, default 0
180
181 switch (idx) {
182 case AlphaISA::IPR_PALtemp0:
183 case AlphaISA::IPR_PALtemp1:

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337 // isa_desc).
338 ipr[idx] = val;
339 break;
340
341 case AlphaISA::IPR_PALtemp23:
342 // write entire quad w/ no side-effect
343 old = ipr[idx];
344 ipr[idx] = val;
345#if FULL_SYSTEM
346 if (tc->getKernelStats())
347 tc->getKernelStats()->context(old, val, tc);
348#endif
349 break;
350
351 case AlphaISA::IPR_DTB_PTE:
352 // write entire quad w/ no side-effect, tag is forthcoming
353 ipr[idx] = val;
354 break;
355
356 case AlphaISA::IPR_EXC_ADDR:

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367 case AlphaISA::IPR_IPLR:
368#ifdef DEBUG
369 if (break_ipl != -1 && break_ipl == (val & 0x1f))
370 debug_break();
371#endif
372
373 // only write least significant five bits - interrupt level
374 ipr[idx] = val & 0x1f;
375#if FULL_SYSTEM
376 if (tc->getKernelStats())
377 tc->getKernelStats()->swpipl(ipr[idx]);
378#endif
379 break;
380
381 case AlphaISA::IPR_DTB_CM:
382#if FULL_SYSTEM
383 if (val & 0x18) {
384 if (tc->getKernelStats())
385 tc->getKernelStats()->mode(TheISA::Kernel::user, tc);
386 } else {
387 if (tc->getKernelStats())
388 tc->getKernelStats()->mode(TheISA::Kernel::kernel, tc);
389 }
390#endif
391
392 case AlphaISA::IPR_ICM:
393 // only write two mode bits - processor mode
394 ipr[idx] = val & 0x18;
395 break;
396
397 case AlphaISA::IPR_ALT_MODE:
398 // only write two mode bits - processor mode

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471 tc->getDTBPtr()->flushProcesses();
472 break;
473
474 case AlphaISA::IPR_DTB_IS:
475 // really a control write
476 ipr[idx] = val;
477
478 tc->getDTBPtr()->flushAddr(val,
479 EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
480 break;
481
482 case AlphaISA::IPR_DTB_TAG: {
483 struct AlphaISA::PTE pte;
484
485 // FIXME: granularity hints NYI...
486 if (EV5::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
487 panic("PTE GH field != 0");
488
489 // write entire quad
490 ipr[idx] = val;
491
492 // construct PTE for new entry
493 pte.ppn = EV5::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
494 pte.xre = EV5::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
495 pte.xwe = EV5::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
496 pte.fonr = EV5::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
497 pte.fonw = EV5::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
498 pte.asma = EV5::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
499 pte.asn = EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
500
501 // insert new TAG/PTE value into data TLB
502 tc->getDTBPtr()->insert(val, pte);
503 }
504 break;
505
506 case AlphaISA::IPR_ITB_PTE: {
507 struct AlphaISA::PTE pte;
508
509 // FIXME: granularity hints NYI...
510 if (EV5::ITB_PTE_GH(val) != 0)
511 panic("PTE GH field != 0");
512
513 // write entire quad
514 ipr[idx] = val;
515
516 // construct PTE for new entry
517 pte.ppn = EV5::ITB_PTE_PPN(val);
518 pte.xre = EV5::ITB_PTE_XRE(val);
519 pte.xwe = 0;
520 pte.fonr = EV5::ITB_PTE_FONR(val);
521 pte.fonw = EV5::ITB_PTE_FONW(val);
522 pte.asma = EV5::ITB_PTE_ASMA(val);
523 pte.asn = EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
524
525 // insert new TAG/PTE value into data TLB
526 tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
527 }
528 break;
529
530 case AlphaISA::IPR_ITB_IA:
531 // really a control write

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541 tc->getITBPtr()->flushProcesses();
542 break;
543
544 case AlphaISA::IPR_ITB_IS:
545 // really a control write
546 ipr[idx] = val;
547
548 tc->getITBPtr()->flushAddr(val,
549 EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
550 break;
551
552 default:
553 // invalid IPR
554 panic("Tried to write to invalid ipr %d\n", idx);
555 }
556
557 // no error...
558}
559
560
561void
562AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
563{
564 for (int i = 0; i < NumInternalProcRegs; ++i) {
565 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
566 }
567}
568
569#if FULL_SYSTEM
570
571/**
572 * Check for special simulator handling of specific PAL calls.
573 * If return value is false, actual PAL call will be suppressed.
574 */
575bool
576SimpleThread::simPalCheck(int palFunc)
577{

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