1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 80 unchanged lines hidden (view full) ---

89void
90AlphaISA::processInterrupts(CPU *cpu)
91{
92 //Check if there are any outstanding interrupts
93 //Handle the interrupts
94 int ipl = 0;
95 int summary = 0;
96
97 if (cpu->readMiscReg(IPR_ASTRR))
98 panic("asynchronous traps not implemented\n");
99
100 if (cpu->readMiscReg(IPR_SIRR)) {
101 for (int i = INTLEVEL_SOFTWARE_MIN;
102 i < INTLEVEL_SOFTWARE_MAX; i++) {
103 if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
104 // See table 4-19 of the 21164 hardware reference

--- 43 unchanged lines hidden (view full) ---

148 if (!(readPC() & 0x3))
149 return new UnimplementedOpcodeFault;
150
151 setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
152
153 if (!misspeculating()) {
154 if (kernelStats)
155 kernelStats->hwrei();
156 }
157
158 // FIXME: XXX check for interrupts? XXX
159 return NoFault;
160}
161
162int
163AlphaISA::MiscRegFile::getInstAsid()

--- 426 unchanged lines hidden ---