1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#include "arch/alpha/tlb.hh"
33#include "arch/alpha/isa_traits.hh"
34#include "arch/alpha/osfpal.hh"
35#include "base/kgdb.h"
36#include "base/remote_gdb.hh"
37#include "base/stats/events.hh"

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143CPUExecContext::hwrei()
144{
145 if (!inPalMode())
146 return new UnimplementedOpcodeFault;
147
148 setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
149
150 if (!misspeculating()) {
151 cpu->kernelStats->hwrei();
152
153 cpu->checkInterrupts = true;
154 }
155
156 // FIXME: XXX check for interrupts? XXX
157 return NoFault;
158}
159

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333 // isa_desc).
334 ipr[idx] = val;
335 break;
336
337 case AlphaISA::IPR_PALtemp23:
338 // write entire quad w/ no side-effect
339 old = ipr[idx];
340 ipr[idx] = val;
341 xc->getCpuPtr()->kernelStats->context(old, val, xc);
342 break;
343
344 case AlphaISA::IPR_DTB_PTE:
345 // write entire quad w/ no side-effect, tag is forthcoming
346 ipr[idx] = val;
347 break;
348
349 case AlphaISA::IPR_EXC_ADDR:

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360 case AlphaISA::IPR_IPLR:
361#ifdef DEBUG
362 if (break_ipl != -1 && break_ipl == (val & 0x1f))
363 debug_break();
364#endif
365
366 // only write least significant five bits - interrupt level
367 ipr[idx] = val & 0x1f;
368 xc->getCpuPtr()->kernelStats->swpipl(ipr[idx]);
369 break;
370
371 case AlphaISA::IPR_DTB_CM:
372 if (val & 0x18)
373 xc->getCpuPtr()->kernelStats->mode(Kernel::user, xc);
374 else
375 xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc);
376
377 case AlphaISA::IPR_ICM:
378 // only write two mode bits - processor mode
379 ipr[idx] = val & 0x18;
380 break;
381
382 case AlphaISA::IPR_ALT_MODE:
383 // only write two mode bits - processor mode

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553
554/**
555 * Check for special simulator handling of specific PAL calls.
556 * If return value is false, actual PAL call will be suppressed.
557 */
558bool
559CPUExecContext::simPalCheck(int palFunc)
560{
561 cpu->kernelStats->callpal(palFunc, proxy);
562
563 switch (palFunc) {
564 case PAL::halt:
565 halt();
566 if (--System::numSystemsRunning == 0)
567 new SimExitEvent("all cpus halted");
568 break;
569
570 case PAL::bpt:
571 case PAL::bugchk:
572 if (system->breakpoint())
573 return false;
574 break;
575 }
576
577 return true;
578}
579
580#endif // FULL_SYSTEM