1/*
2 * Copyright (c) 2012 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ALPHA_DECODER_HH__
32#define __ARCH_ALPHA_DECODER_HH__
33
| 1/*
2 * Copyright (c) 2012 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ALPHA_DECODER_HH__
32#define __ARCH_ALPHA_DECODER_HH__
33
|
| 34#include "arch/generic/decode_cache.hh"
|
34#include "arch/types.hh"
| 35#include "arch/types.hh"
|
35#include "cpu/decode_cache.hh"
36#include "cpu/static_inst_fwd.hh"
| 36#include "cpu/static_inst.hh"
|
37#include "sim/full_system.hh"
38
| 37#include "sim/full_system.hh"
38
|
| 39class ThreadContext;
40
|
39namespace AlphaISA
40{
41
42class Decoder
43{
44 protected:
45 ThreadContext *tc;
46
47 // The extended machine instruction being generated
48 ExtMachInst ext_inst;
49 bool instDone;
50
51 public:
52 Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
53 {}
54
55 ThreadContext *
56 getTC()
57 {
58 return tc;
59 }
60
61 void
62 setTC(ThreadContext * _tc)
63 {
64 tc = _tc;
65 }
66
67 void
68 process()
69 { }
70
71 void
72 reset()
73 {
74 instDone = false;
75 }
76
77 // Use this to give data to the predecoder. This should be used
78 // when there is control flow.
79 void
80 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
81 {
82 ext_inst = inst;
83 instDone = true;
84 if (FullSystem)
85 ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
86 }
87
88 bool
89 needMoreBytes()
90 {
91 return true;
92 }
93
94 bool
95 instReady()
96 {
97 return instDone;
98 }
99
100 protected:
101 /// A cache of decoded instruction objects.
| 41namespace AlphaISA
42{
43
44class Decoder
45{
46 protected:
47 ThreadContext *tc;
48
49 // The extended machine instruction being generated
50 ExtMachInst ext_inst;
51 bool instDone;
52
53 public:
54 Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
55 {}
56
57 ThreadContext *
58 getTC()
59 {
60 return tc;
61 }
62
63 void
64 setTC(ThreadContext * _tc)
65 {
66 tc = _tc;
67 }
68
69 void
70 process()
71 { }
72
73 void
74 reset()
75 {
76 instDone = false;
77 }
78
79 // Use this to give data to the predecoder. This should be used
80 // when there is control flow.
81 void
82 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
83 {
84 ext_inst = inst;
85 instDone = true;
86 if (FullSystem)
87 ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
88 }
89
90 bool
91 needMoreBytes()
92 {
93 return true;
94 }
95
96 bool
97 instReady()
98 {
99 return instDone;
100 }
101
102 protected:
103 /// A cache of decoded instruction objects.
|
102 static DecodeCache defaultCache;
| 104 static GenericISA::BasicDecodeCache defaultCache;
|
103
104 public:
105 StaticInstPtr decodeInst(ExtMachInst mach_inst);
106
107 /// Decode a machine instruction.
108 /// @param mach_inst The binary instruction to decode.
109 /// @retval A pointer to the corresponding StaticInst object.
110 StaticInstPtr
111 decode(ExtMachInst mach_inst, Addr addr)
112 {
113 return defaultCache.decode(this, mach_inst, addr);
114 }
115
116 StaticInstPtr
117 decode(AlphaISA::PCState &nextPC)
118 {
119 if (!instDone)
120 return NULL;
121 instDone = false;
122 return decode(ext_inst, nextPC.instAddr());
123 }
124};
125
126} // namespace AlphaISA
127
128#endif // __ARCH_ALPHA_DECODER_HH__
| 105
106 public:
107 StaticInstPtr decodeInst(ExtMachInst mach_inst);
108
109 /// Decode a machine instruction.
110 /// @param mach_inst The binary instruction to decode.
111 /// @retval A pointer to the corresponding StaticInst object.
112 StaticInstPtr
113 decode(ExtMachInst mach_inst, Addr addr)
114 {
115 return defaultCache.decode(this, mach_inst, addr);
116 }
117
118 StaticInstPtr
119 decode(AlphaISA::PCState &nextPC)
120 {
121 if (!instDone)
122 return NULL;
123 instDone = false;
124 return decode(ext_inst, nextPC.instAddr());
125 }
126};
127
128} // namespace AlphaISA
129
130#endif // __ARCH_ALPHA_DECODER_HH__
|