1# -*- mode:python -*- 2 3# Copyright (c) 2004-2005 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 119 unchanged lines hidden (view full) --- 128 mem/cache/tags/split_lru.cc 129 130 mem/cache/cache_builder.cc 131 132 python/swig/init.cc 133 python/swig/debug_wrap.cc 134 python/swig/main_wrap.cc 135 python/swig/event_wrap.cc |
136 python/swig/trace_wrap.cc |
137 python/swig/pyevent.cc 138 139 sim/builder.cc 140 sim/debug.cc 141 sim/eventq.cc 142 sim/faults.cc 143 sim/main.cc 144 sim/param.cc 145 sim/root.cc 146 sim/serialize.cc 147 sim/sim_events.cc 148 sim/sim_object.cc 149 sim/startup.cc 150 sim/stat_context.cc 151 sim/stat_control.cc 152 sim/system.cc |
153 sim/trace_control.cc |
154 ''') 155 156trace_reader_sources = Split(''' 157 cpu/trace/reader/mem_trace_reader.cc 158 cpu/trace/reader/ibm_reader.cc 159 cpu/trace/reader/itx_reader.cc 160 cpu/trace/reader/m5_reader.cc 161 cpu/trace/opt_cpu.cc --- 200 unchanged lines hidden --- |