1# -*- mode:python -*-
2
3# Copyright (c) 2004-2005 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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80 base/stats/statdb.cc
81 base/stats/visit.cc
82 base/stats/text.cc
83
84 cpu/activity.cc
85 cpu/base.cc
86 cpu/cpuevent.cc
87 cpu/exetrace.cc
88 cpu/op_class.cc
89 cpu/pc_event.cc
90 cpu/quiesce_event.cc
91 cpu/static_inst.cc
92 cpu/sampler/sampler.cc
93 cpu/simple_thread.cc
94 cpu/thread_state.cc
95
96 encumbered/cpu/full/fu_pool.cc
97
98 mem/bridge.cc
99 mem/bus.cc
100 mem/mem_object.cc
101 mem/packet.cc
102 mem/physical.cc
103 mem/port.cc
104
105 sim/builder.cc
106 sim/debug.cc
107 sim/eventq.cc
108 sim/faults.cc
109 sim/main.cc
110 python/swig/main_wrap.cc
111 sim/param.cc
112 sim/profile.cc
113 sim/root.cc

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