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< * Copyright (c) 2014-2015 ARM Limited
---
> * Copyright (c) 2014-2016 ARM Limited
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< RegAddr(MMU_IRQ_STATUS)),
< regs(BLOCK_NUM_REGS)
---
> RegAddr(MMU_IRQ_STATUS))
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> spaces.reserve(16);
> for (int i = 0; i < 16; ++i)
> spaces.emplace_back(_gpu, *this, i);
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> MMU::reset()
> {
> GPUBlockInt::reset();
>
> for (auto &as : spaces)
> as.reset();
> }
>
> uint32_t
> MMU::readReg(RegAddr addr)
> {
> if (isAddrSpaceReg(addr)) {
> return spaces[getAddrSpaceNo(addr)].readReg(getAddrSpaceAddr(addr));
> } else {
> return GPUBlockInt::readReg(addr);
> }
> }
>
> void
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< // Ignore writes by default
---
> if (isAddrSpaceReg(addr)) {
> AddrSpace &as(spaces[getAddrSpaceNo(addr)]);
> as.writeReg(getAddrSpaceAddr(addr), value);
> }
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> uint32_t
> MMU::readRegRaw(RegAddr addr)
> {
> if (isAddrSpaceReg(addr)) {
> return spaces[getAddrSpaceNo(addr)].readRegRaw(getAddrSpaceAddr(addr));
> } else {
> return GPUBlockInt::readRegRaw(addr);
> }
> }
>
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> MMU::writeRegRaw(RegAddr addr, uint32_t value)
> {
> if (isAddrSpaceReg(addr)) {
> spaces[getAddrSpaceNo(addr)].writeRegRaw(getAddrSpaceAddr(addr), value);
> } else {
> GPUBlockInt::writeRegRaw(addr, value);
> }
> }
>
> void